mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 41

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

RW_CC# is an HCS12 interface read/write input signal. It indicates the direction of data transfer for a
transaction.
2.4.3.10 A10/ECLK_CC — AMI Address Bus, HCS12 Clock Input
The function of this pin is selected by the IF_SEL[1:0] pins. Refer
for more information. The pin can be configured to enable or disable either a pullup or pulldown resistor
on the pin.
A10 is an AMI interface address signal.
ECLK_CC is the HCS12 interface clock input signal. (The maximum frequency of this signal can be
calculated from the ECLK pulse width low and high times, t
2.4.3.11 RXD_BG[2:1] — PHY Data Receiver Inputs
RXD_BG[2:1] are bus driver receive data input signals if the FlexRay Optical/Electrical PHY is
configured:
These pins can be configured to enable or disable either pullup or pulldown resistors on the pins.
2.4.3.12 TXEN[2:1]# — PHY Transmit Enable
TXEN[2:1]# are bus driver transmit enable output signals if the FlexRay Optical/Electrical PHY is
configured:
These pins can be configured to provide either high or reduced output drive.
2.4.3.13 TXD_BG[1:2]/IF_SEL[1:0] — PHY Transmit Data Outputs, Host Interface
These pins can be configured to provide either high or reduced output drive.
TXD_BG[1:2] are bus driver transmit data output signals if the FlexRay Optical/Electrical PHY is
configured:
IF_SEL[1:0] are the CC external interface selection input signals. Refer to
coding.
Freescale Semiconductor
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RXD_BG1 is the input to the CC from Physical Layer Channel 1
RXD_BG2 is the input to the CC from Physical Layer Channel 2
TXEN1# is the output of the CC to Physical Layer Channel 1
TXEN2# is the output of the CC to Physical Layer Channel 2
TXD_BG1 is the output of the CC to Physical Layer Channel 1
TXD_BG2 is the output of the CC to Physical Layer Channel 2
Selection
The IF_SEL[1:0] signals are inputs during the internal reset sequence and
are latched during the internal reset sequence.
MFR4300 Data Sheet, Rev. 3
NOTE
LEC
and t
Section 2.7, “External Host
HEC
given in
Table 2-6
Table
for the selection
A-14.)
Device Overview
Interface”
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