mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 82

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

FlexRay Module (FLEXRAYV2)
3.3.2.13
This register defines whether the interrupt flags defined in the
can generate a interrupt request.
82
0x001C
Reset
SSI[3:0]_IF
MRC_IE
FATL_IE
INTL_IE
ILCF_IE
PSC_IF
ODT_IF
CSA_IE
EVT_IF
W
Field
Field
11–8
R
12
15
14
13
12
11
5
4
15
0
Protocol State Changed Interrupt Flag — This flag is set when the protocol state in the PROTSTATE field in
the
0 No such event.
1 Protocol state changed.
Slot Status Counter Incremented Interrupt Flag — Each of these flags is set when the SLOTSTATUSCNT
field in the corresponding
0 No such event.
1 The corresponding slot status counter has incremented.
Even Cycle Table Written Interrupt Flag — This flag is set if the FlexRay module has written the sync frame
measurement / ID tables into the FRM for the even cycle.
0 No such event.
1 Sync frame measurement table written
Odd Cycle Table Written Interrupt Flag — This flag is set if the FlexRay module has written the sync frame
measurement / ID tables into the FRM for the odd cycle.
0 No such event.
1 Sync frame measurement table written
Fatal Protocol Error Interrupt Enable — This bit controls FATL_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Internal Protocol Error Interrupt Enable — This bit controls INTL_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Illegal Protocol Configuration Interrupt Enable — This bit controls ILCF_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Cold Start Abort Interrupt Enable — This bit controls CSA_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Missing Rate Correction Interrupt Enable — This bit controls MRC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Protocol Interrupt Enable Register 0 (PIER0)
14
0
Protocol Status Register 0 (PSR0)
13
0
Figure 3-12. Protocol Interrupt Enable Register 0 (PIER0)
12
0
Table 3-18. PIFR1 Field Descriptions (Sheet 2 of 2)
11
0
Slot Status Counter Registers (SSCR0–SSCR3)
Table 3-19. PIER0 Field Descriptions
10
0
MFR4300 Data Sheet, Rev. 3
has changed.
0
9
0
8
Description
Description
0
7
Protocol Interrupt Flag Register 0 (PIFR0)
6
0
0
5
is
0
4
incremented.
0
3
Freescale Semiconductor
0
2
Write: Any Time
1
0
0
0