mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 33

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

2.3.1
Table 2-1
1
2
3
Freescale Semiconductor
0x00A0–0x00DE
0x00E4–0x00EE
0x004C–0x0058
0x008C–0x008E
0x009C, 0x009E
0x00E0–0x00E2
0x00F0–0x00FE
0x0100–0x01FE
0x0200–0x02FE
0x0300–0x03FE
0x0400–0x04FE
0x0500–0x07FE
0x0800–0x1FFE
0x0000–0x000E
0x0028–0x003E
0x0046–0x004A
0x005A–0x0062
0x0068–0x007E
0x0086–0x008A
0x0090–0x009A
0x0010–0x0012
0x0014–0x0026
0x0040–0x0044
0x0064–0x0066
0x0080–0x0082
address (Hex)
For detailed information on the MFR4300 FlexRay module registers, see
For detailed information on the MFR4300 CRG module registers, see
For detailed information on the MFR4300 PIM module registers, see
0x0084
shows the MFR4300 device memory map.
Memory Map
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
FlexRay
Module
CRG
PIM
3
2
1
Table 2-1. MFR4300 Device Memory Map After Reset
Configuration and Control Registers
Reserved
Interrupt and Error Handling Registers
Protocol Status Registers
Sync Frame Counter and Table Registers
Sync Frame Filter Registers
Network Management Vector Registers
Timer Configuration Registers
Slot Status Configuration Registers
Slot Status and Slot Status Counter Registers
MTS Generation Registers
Shadow Buffer Configuration Register
Receive FIFO — Configuration
Receive FIFO — Status
Receive FIFO — Filter
Dynamic Segment Status Registers
Protocol Configuration Registers
Clock and Reset Generation Registers
Reserved
Part ID, ASIC Version Number, and Interface Pin Drive Strength and
Pullup/pulldown Control and Enable Registers
Message Buffers Configuration, Control, Status (Message Buffer 0–31)
Message Buffers Configuration, Control, Status (Message Buffer 32–63)
Message Buffers Configuration, Control, Status (Message Buffer 64–95)
Message Buffers Configuration, Control, Status (Message Buffer 96–127)
Reserved
Message Buffers and FIFO Frame Header/Offset/Status/Data
MFR4300 Data Sheet, Rev. 3
Registers
Chapter 4, “Port Integration Module
Chapter 6, “Clocks and Reset Generator
Chapter 3, “FlexRay Module
(FLEXRAYV2)”.
(PIM)”.
Device Overview
(CRG)”.
(bytes)
6144
Size
256
256
256
256
768
16
20
24
14
10
24
12
64
12
16
4
6
6
4
4
2
6
4
4
4
33