SST25VF040-20-4C-QAE SST [Silicon Storage Technology, Inc], SST25VF040-20-4C-QAE Datasheet - Page 12

• Manufacturer Part Number: SST25VF040-20-4C-QAE
• Description: 4 Mbit SPI Serial Flash
• Manufacturer: SST [Silicon Storage Technology, Inc]

EOL Product Data Sheet
Chip-Erase
The Chip-Erase instruction clears all bits in the device to
FFH. A Chip-Erase instruction will be ignored if any of the
memory area is protected. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of the Chip-Erase
instruction sequence. The Chip-Erase instruction is initiated
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows read-
ing of the status register. The status register may be read at
any time even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that
the new commands are properly received by the device.
©2006 Silicon Storage Technology, Inc.
FIGURE 10: Chip-Erase Sequence
FIGURE 11: Read-Status-Register (RDSR) Sequence
SCK
CE#
SO
SI
MODE 3
MODE 0
MSB
0
1
HIGH IMPEDANCE
2
SCK
CE#
3
SO
SI
05
MODE 3
MODE 0
4
5
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7
6
12
7
by executing an 8-bit command, 60H. CE# must be driven
high before the instruction is executed. The user may poll
the Busy bit in the software status register or wait T
the completion of the internal self-timed Chip-Erase cycle.
See Figure 10 for the Chip-Erase sequence.
CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-
Status-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE#.
See Figure 11 for the RDSR instruction sequence.
60
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
8
1231 F09.1
9
10
Register Out
11
Status
12
4 Mbit SPI Serial Flash
13
14
1231 F10.1
SST25VF040
S71231(04)-01-EOL
CE
09/10
for