HD3-15531B-9 INTERSIL [Intersil Corporation], HD3-15531B-9 Datasheet - Page 3

• Manufacturer Part Number: HD3-15531B-9
• Description: CMOS Manchester Encoder-Decoder
• Manufacturer: INTERSIL [Intersil Corporation]

Pin Description
NUMBER
PIN
10
11
12
13
1
2
3
4
5
6
7
8
9
TYPE
O
O
O
O
I
I
I
I
I
I
I
I
SYNCHRONOUS
SYNCHRONOUS
CLK SELECT
CLK SELECT
V
VALID WORD
TAKE DATA’
TAKE DATA
SERIAL DATA OUT
SYNCHRONOUS
DATA
SYNCHRONOUS
DATA SELECT
SYNCHRONOUS
CLOCK
DECODER CLOCK
SYNCHRONOUS
CLOCK SELCT
BIPOLAR ZERO IN
BIPOLAR ONE IN
UNIPOLAR DATA IN
UNIPOLAR
CC
DECODER
DECODER
BIPOLAR
BIPOLAR
DATA IN
MASTER
ONE IN
ONE IN
RESET
NAME
CLK
CLK
11
15 SYNCHRONIZER
10
22
13
12
9
8
SYNCHRONOUS
TRANSITION
DATA SELECT
FINDER
SECTION
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Both
Positive supply pin. A 0.1µF decoupling capacitor from V
(pin 21) is recommended.
Output high indicates receipt of a valid word, (valid parity and no Manchester
errors).
A continuous, free running signal provided for host timing or data handling. When
data is present on the bus, this signal will be synchronized to the incoming data
and will be identical to TAKE DATA.
Output is high during receipt of data after identification of a valid sync pulse and
two valid Manchester bits.
Delivers received data in correct NRZ format.
Input presents Manchester data directly to character identification logic.
SYNCHRONOUS DATA SELECT must be held high to use this input. If not
used, this pin must be held high.
In high state allows the synchronous data to enter the character identification
logic. Tie this input low for asynchronous data.
Input provides externally synchronized clock to the decoder, for use when re-
ceiving synchronous data. This input must be tied high when not in use.
Input drives the transition finder, and the synchronizer which in turn supplies the
clock to the balance of the decoder. Input a frequency equal to 12X the data rate.
In high state directs the SYNCHRONOUS CLOCK to control the decoder char-
acter identification logic. A low state selects the DECODER CLOCK.
A high input should be applied when the bus is in its negative state. This pin must
be held high when the unipolar input is used.
A high input should be applied when the bus is in its positive state. This pin must
he held low when the unipolar input is used.
With pin 11 high and pin 12 low, this pin enters unipolar data into the transition
finder circuit. If not used this input must be held low.
DECODER
7
HD-15531
SELECT
CLOCK
RESET
DECODER
SELECT
DATA
GATE
DATA
3
19
8
20 40
C
SYNCHRONOUS
DATA
0
RATE
CLK
BIT
C
CHARACTER
COUNTER
IDENTIFIER
1
23
BIT
C
2
36
PARITY
CHECK
DESCRIPTION
C
3
39
C
4
14
17
16
4
5
2
3
TAKE DATA
COMMAND SYNC
DATA SYNC
SERIAL
DATA OUT
VALID WORD
PARITY
SELECT
DECODER
SHIFT CLK
TAKE DATA’
CC
(pin 1) to GROUND