HD3-15531B-9 INTERSIL [Intersil Corporation], HD3-15531B-9 Datasheet - Page 5

• Manufacturer Part Number: HD3-15531B-9
• Description: CMOS Manchester Encoder-Decoder
• Manufacturer: INTERSIL [Intersil Corporation]

Encoder Operation
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SEND CLOCK
input. An auxiliary divide by six counter is provided on chip
which can be utilized to produce the SEND CLOCK by divid-
ing the DECODER CLOCK. The frame length is set by pro-
gramming the COUNT inputs. Parity is selected by
programming ENCODER PARITY SELECT high for odd par-
ity or low for even parity.
The Encoder’s cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK
This cycle lasts for one word length or K + 4 ENCODER
SHIFT CLOCK periods, where K is the number of bits to be
sent. At the next low-to-high transition of the ENCODER
SHIFT CLOCK, a high SYNC SELECT input actuates a
Command sync or a low will produce a Data sync for the
word
SEND DATA output will go high for K ENCODER SHIFT
CLOCK periods
Decoder Operation
To operate the Decoder asynchronously requires a single
clock with a frequency of 12 times the desired data rate
applied at the DECODER CLOCK input. To operate the
Decoder
CLOCK at a frequency 2 times the data rate which is syn-
chronized with the data at every high-to-low transition
applied to the SYNCHRONOUS CLK input. The Manchester
II coded data can be presented to the Decoder asynchro-
nously in one of two ways. The BIPOLAR ONE and
BIPOLAR ZERO inputs will accept data from a comparator
sensed transformer coupled bus as specified in Military Spec
1553. The UNIPOLAR DATA input can only accept nonin-
verted Manchester II coded data. (e.g., from BIPOLAR ONE
SHIFT CLOCK
SEND CLOCK
ZERO OUT
ENCODER
ENCODER
ONE OUT
BIPOLAR
BIPOLAR
ENABLE
SELECT
DATA IN
SERIAL
2
TIMING
SYNC
SEND
DATA
. When the Encoder is ready to accept data, the
synchronously
4
. During these K periods the data should
1
VALID
2
requires
1ST HALF 2ND HALF MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4
SYNC
0
1
a
SYNC
3
2
SYNCHRONOUS
MSB
DON’T CARE
DON’T CARE
MSB BIT K-1
3
BIT K-1
FIGURE 1. ENCODER
4
BIT K-2
HD-15531
BIT K-2 BIT K-3 BIT K-4
1
5
.
BIT K-3 BIT K-4 BIT K-5 BIT 4
5
be clocked into the SERIAL DATA input with every high-to-
low transition of the ENCODER SHIFT CLOCK
can be sampled on the low-to-high transition. After the sync
and Manchester II encoded data are transmitted through the
BIPOLAR ONE and BIPOLAR ZERO outputs, the Encoder
adds on an additional bit with the parity for that word
ENCODER ENABLE is held high continuously, consecutive
words will be encoded without an interframe gap.
ENCODER ENABLE must go low by time
prevent a consecutive word from being encoded. At any time
a low on OUTPUT INHIBIT input will force both bipolar out-
puts to a high state but will not affect the Encoder in any
other way.
To abort the Encoder transmission, a positive pulse must be
applied at MASTER RESET. Any time after or during this
pulse, a low-to-high transition on SEND CLOCK clears the
internal counters and initializes the Encoder for a new word.
OUT on an Encoder through an inverter to Unipolar Data
Input).
The Decoder is free running and continuously monitors its
data input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized
level at either COMMAND SYNC or DATA SYNC output. If
the sync character was a command sync the COMMAND
SYNC output will go high
CLOCK periods
received. If the sync character was a data sync, the DATA
SYNC output will go high. The TAKE DATA output will go
high and remain high
6
7
BIT 4
BIT 4
3
N-4
1
, where K is the number of bits to be
BIT 3
, the type of sync is indicated by a high
2
BIT 3
BIT 3
N-3
-
BIT 2
2
3
BIT 2
BIT 2
N-2
while the Decoder is transmit-
and remain high for K SHIFT
BIT 1
BIT 1
BIT 1 PARITY
N-1
4 5
PARITY
N
5
(as shown) to
3
-
4
5
so it
. If