SST49LF040-33-4C-WH SST [Silicon Storage Technology, Inc], SST49LF040-33-4C-WH Datasheet
SST49LF040-33-4C-WH
Related parts for SST49LF040-33-4C-WH
SST49LF040-33-4C-WH Summary of contents
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... Erase and Program time increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST49LF040 device is offered in 32-lead TSOP and 32- lead PLCC packages. See Figures 2 and 3 for pin assign- ments and Table 1 for pin descriptions. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ...
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... Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Software Data Protection (SDP ©2001 Silicon Storage Technology, Inc. 4 Mbit LPC Flash 2 SST49LF040 Advance Information S71213-00-000 11/01 562 ...
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... Mbit LPC Flash SST49LF040 Advance Information Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC CHARACTERISTICS (LPC MODE CHARACTERISTICS (PP MODE PRODUCT ORDERING INFORMATION Valid combinations for SST49LF040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 ©2001 Silicon Storage Technology, Inc. 3 S71213-00-000 11/01 562 ...
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... LIST OF FIGURES FIGURE 1: Device Memory Map for SST49LF040 FIGURE 2: Pin Assignments for 32-lead TSOP (8mm x 14mm FIGURE 3: Pin Assignments for 32-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 4: Boot Configuration from the Top of the 4 GByte System Memory Map FIGURE 5: Boot Configuration from the Bottom of the 4 GByte System Memory Map . . . . . . . . . . . . . . . . 12 FIGURE 6: LCLK Waveform ...
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... SST49LF040 Advance Information LIST OF TABLES TABLE 1: Pin Description TABLE 2: ID Strapping Values for SST49LF040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TABLE 3: General Purpose Inputs Register TABLE 4: Memory Map Register Addresses (Top of the 4GB System Memory TABLE 5: Memory Map Register Addresses (Bottom of the 4GB System Memory TABLE 6: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 7: Operation Modes Selection (PP Mode) ...
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... Block 0 03000H (64 KByte) 02000H 01000H 00000H SST49LF040 AP FOR 6 4 Mbit LPC Flash SST49LF040 Advance Information SuperFlash Memory Y-Decoder I/O Buffers and Data Latches 562 ILL B1.0 Boot Block 4 KByte Sector 15 4 KByte Sector 2 4 KByte Sector 1 4 KByte Sector 0 562 ILL F03.0 ...
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... Mbit LPC Flash SST49LF040 Advance Information PIN DESCRIPTION (CE#) 4 MODE (MODE) 5 A10 (GPI4) 6 R/C# (LCLK RST# (RST (GPI3 (GPI2 (GPI1 (GPI0 (WP (TBL Designates LPC Mode FIGURE SSIGNMENTS FOR ...
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... CE# must remain low during internal Write (Program or Erase) operations. When CE# is high, the device is placed in low power Standby mode Unconnected pins Mbit LPC Flash SST49LF040 Advance Information ) for PP mode and low (V ) for LPC mode T1.4 562 S71213-00-000 11/01 562 ...
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... The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of device mem- ory in the SST49LF040. The TBL# pin is used to write pro- tect 16 boot sectors (64 KByte) at the highest memory address range for the SST49LF040. WP# pin write pro- tects the remaining sectors in the flash memory. © ...
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... CE# must be asserted one cycle before the start cycle to select the SST49LF040 for Read and Write operations. Once the SST49LF040 identifies the operation as valid (a start value of all zeros), it next expects a nibble that indi- cates whether this is a memory Read or Write cycle. Once this is received, the device is now ready for the Address and Data cycles ...
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... Address bits A -A decoding for multiple device selection 22 19 depends on whether the device is mapped from the top of the 4GB system memory map or from the bottom of the 4GB system memory map. ©2001 Silicon Storage Technology, Inc. SST49LF040 - Decoding Bottom 0001b ...
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... General Purpose Inputs Register The GPI_REG (General Purpose Inputs Register) passes the state of GPI[4:0] pins at power-up on the SST49LF040 recommended that the GPI[4:0] pins be in the desired state before LFRAME# is brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle ...
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... Mbit LPC Flash SST49LF040 Advance Information JEDEC ID Registers The JEDEC ID registers identify the device as SST49LF040 and manufacturer as SST in LPC mode. See Tables 4 and 5 for memory address location for its respec- TABLE EMORY AP EGISTER Device # ...
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... R/C# and the column address is latched on the rising edge of R/C#. Read The Read operation of the SST49LF040 device is con- trolled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle tim- ing diagram, Figure 19, for further details. ...
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... Mbit LPC Flash SST49LF040 Advance Information Data# Polling ( When the SST49LF040 device is in the internal Program operation, any attempt to read DQ will produce the com- 7 plement of the true data. Once the Program operation is completed, DQ will produce true data. Note that even ...
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... Program IH V Erase IH Reset Write Inhibit Product Identification can but no other value Device ID 51H for SST49LF040 TABLE OFTWARE OMMAND 1 1st Cycle Command 2 Sequence Addr Data Addr Byte- YYYY 5555H AAH YYYY 2AAAH Program Sector- ...
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... I Standby V Current SB DD (LPC Interface Ready Mode V Current (LPC Interface Input Current for IC: I ID[3:0] pins for SST49LF040 ID[3:1] pins for SST49LF080A I Input Leakage Current LI I Output Leakage Current LO V INIT# Input High Voltage IHI V INIT# Input Low Voltage ILI V Input Low Voltage ...
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... Specification 10,000 100 100 + I DD (LPC M ) ODE Min cyc T high 0 Mbit LPC Flash SST49LF040 Advance Information Units 100 µs 100 µs Maximum = I/O = Units Test Method Cycles JEDEC Standard A117 Years JEDEC Standard A103 ...
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... Mbit LPC Flash SST49LF040 Advance Information TABLE 14 ESET IMING ARAMETERS Symbol Parameter T V stable to Reset Low PRST DD T Clock Stable to Reset Low KRST T RST# Pulse Width RSTP T RST# Low to Output Float RSTF 1 T RST# High to LFRAME# Low RST T RST# Low to reset during Sector-/Block-Erase or Program RSTE 1 ...
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... V DD -17.1 OUT Equation C - Equation D DD 26.7 V OUT -25+(V +1)/0.015 IN 25+(V -V -1)/0.015 Mbit LPC Flash SST49LF040 Advance Information =3.0-3.6V DD Min Max Units Conditions ≤ 0. < V OUT DD mA 0.3V < V < 0.9V DD OUT 1 0.7V < ...
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... Mbit LPC Flash SST49LF040 Advance Information (Valid Output Data) (Float Output Data) FIGURE UTPUT IMING ARAMETERS LCLK LAD [3:0] (Valid Input Data) FIGURE NPUT IMING ARAMETERS ©2001 Silicon Storage Technology, Inc. V LCLK TEST T VAL LAD [3:0] LAD [3: OFF ...
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... Synchronize to host or peripheral by adding wait states. “0000b” means Ready, “0101b” means Short Wait, “0110b” means Long Wait, “1001b” for DMA only, “1010b” means error, other values are reserved. The SST49LF040 only supports “Ready” sync. Data 2 Data Phase for Memory Cycle ...
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... Mbit LPC Flash SST49LF040 Advance Information LCLK CE# RST# LFRAME# Memory Read Start Cycle LAD[3:0] 0000b 010Xb A[31:28] A[27:24] 1 Clock 1 Clock FIGURE 10 EAD YCLE IMING LCLK CE# RST# LFRAME# Memory Write Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock FIGURE 11 RITE YCLE IMING © ...
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... A[3:0] Load Ain in 8 Clocks Write the 4th command (target locations to be programmed) to the device in LPC mode. D (LPC M ) IMING IAGRAM ODE 24 4 Mbit LPC Flash SST49LF040 Advance Information Data TAR Sync TAR 1010b 1010b 1111b Tri-State 0000b Load Data "AAH" Clocks ...
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... Mbit LPC Flash SST49LF040 Advance Information LCLK RST# CE# LFRAME# Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock LCLK RST CE LFRAME# Memory Read Start Cycle LAD[3:0] 0000b 010Xb 1 Clock 1 Clock LCLK RST CE LFRAME# Memory Read Start ...
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... Read the see if internal write complete or not. Address 1 A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] Load Address in 8 Clocks When internal write complete, the DQ 6 will stop toggle. D (LPC M ) IAGRAM ODE 26 4 Mbit LPC Flash SST49LF040 Advance Information Data TAR Sync TAR D[3:0] D[7:4] 1111b Tri-State 0000b Load Data in 2 Clocks 2 Clocks 1 Clock TAR Sync Data ...
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... Mbit LPC Flash SST49LF040 Advance Information LCLK RST# CE# LFRAME# Memory 1st Start LAD[3:0] 0000b 1 Clock 1 Clock LCLK RST CE LFRAME# Memory 2nd Start LAD[3:0] 0000b 1 Clock 1 Clock LCLK RST CE LFRAME# Memory 3rd Start 0000b 011Xb LAD[3:0] 1 Clock 1 Clock ...
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... A[31:28] A[27:24] A[23:20] A[19:16 XXXXb XXXXb XXXXb 0000b Load Block Address in 8 Clocks Load Data “50” Clocks D (LPC M ) IAGRAM ODE 28 4 Mbit LPC Flash SST49LF040 Advance Information Start next Data TAR Sync Command TAR 1010b 1111b Tri-State 0000b 1 Clock 2 Clocks 1 Clock Start next ...
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... Mbit LPC Flash SST49LF040 Advance Information LCLK RST# CE# LFRAME# Memory Read Start Cycle LAD[3:0] 0000b 010Xb 1 Clock 1 Clock Note: See Tables 4 and 5 Register Addresses FIGURE 17: GPI R R EGISTER EADOUT ©2001 Silicon Storage Technology, Inc. Address 1 A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] Load Address in 8 Clocks T D (LPC M ...
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... ARAMETERS ODE DD Min 270 (PP M IMING ARAMETERS ODE Min 100 100 Mbit LPC Flash SST49LF040 Advance Information Max Units ns µ 120 =3.0-3.6V DD Max Units 40 40 150 100 ...
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... Mbit LPC Flash SST49LF040 Advance Information TABLE 21 ESET IMING ARAMETERS Symbol Parameter T V stable to Reset Low PRST DD T RST# Pulse Width RSTP T RST# Low to Output Float RSTF 1 T RST# High to Row Address Setup RST T RST# Low to reset during Sector-/Block-Erase or Program ...
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... Column Address CWH T OES Data Valid D ( IAGRAM ODE 32 4 Mbit LPC Flash SST49LF040 Advance Information Row Address Column Address OHZ High-Z Data Valid 562 ILL F19.0 T OEH T WPH DH 562 ILL F20.0 S71213-00-000 11/01 562 ...
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... Mbit LPC Flash SST49LF040 Advance Information Addresses Row R/C# WE# OE FIGURE 21 ATA OLLING IMING Row Column Addresses R/C# WE# OE FIGURE 22 OGGLE IT IMING ©2001 Silicon Storage Technology, Inc. Column T OEP IAGRAM ODE T OET D ( IAGRAM ODE ...
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... ODE Six-Byte code for Sector-Erase 2AAA 5555 5555 2AAA ( IAGRAM ODE 34 4 Mbit LPC Flash SST49LF040 Advance Information Internal Program Starts Data 562 ILL F23 Internal Erase Starts 55 30 562 ILL F24.0 S71213-00-000 11/01 562 ...
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... Mbit LPC Flash SST49LF040 Advance Information Addresses 5555 R/C# OE WE# T WPH DQ 7 Block Address FIGURE 25 LOCK RASE IMING Addresses 5555 R/C# OE WE# DQ 7-0 AA FIGURE 26 HIP RASE IMING ©2001 Silicon Storage Technology, Inc. Six-Byte code for Block-Erase ...
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... Three-byte sequence for Software ID Entry ADDRESS A 14-0 5555 2AAA R/C# OE WE# DQ 7-0 AA Device ID = 51H for SST49LF040A and 5BH for SST49LF080A FIGURE 27 OFTWARE NTRY AND Three-Byte Sequence for Software ID Exit and Reset ADDRESS A 14-0 5555 R/C# OE WE# DQ 7-0 AA FIGURE 28 OFTWARE XIT AND © ...
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... Mbit LPC Flash SST49LF040 Advance Information V IHT INPUT V ILT AC test inputs are driven at V (0.9 IHT points for inputs and outputs are V FIGURE 29 NPUT UTPUT TO DUT FIGURE 30 EST OAD XAMPLE ©2001 Silicon Storage Technology, Inc REFERENCE POINTS ) for a logic “ ...
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... FIGURE 31 EAD OMMAND (LPC M ) ODE ©2001 Silicon Storage Technology, Inc. FIGURE 32: B EQUENCE 38 4 Mbit LPC Flash SST49LF040 Advance Information Address: 5555H Write Data: AAH Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 5555H Write Data: A0H Cycle: 3 Address ...
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... Mbit LPC Flash SST49LF040 Advance Information Command Sequence Address: 2AAAH Address: 2AAAH FIGURE 33 RASE OMMAND ©2001 Silicon Storage Technology, Inc. Block-Erase Sector-Erase Command Sequence Address: 5555H Address: 5555H Write Data: AAH Write Data: AAH Cycle: 1 Cycle: 1 Address: 2AAAH Write Data: 55H ...
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... Available for Next Command Note: X can but no other value (LPC M OMMAND LOWCHARTS ODE 40 4 Mbit LPC Flash SST49LF040 Advance Information Address: XXXXH Write Data: F0H Cycle: 1 Wait T IDA Available for Next Command 562 ILL F34.0 ) S71213-00-000 11/01 562 ...
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... Mbit LPC Flash SST49LF040 Advance Information FIGURE 35 YTE ROGRAM LGORITHM ©2001 Silicon Storage Technology, Inc. Start Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (T ...
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... Byte- Program/Erase Initiated Read byte Read same byte No Does DQ 6 match? Yes Program/Erase Completed ) ODE 42 4 Mbit LPC Flash SST49LF040 Advance Information Data# Polling Byte- Program/Erase Initiated Read true data? Yes Program/Erase Completed 562 ILL F36.0 S71213-00-000 11/01 562 ...
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... Mbit LPC Flash SST49LF040 Advance Information Software Product ID Entry Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 90H Address: 5555H Wait T IDA Read Software ID FIGURE 37 OFTWARE RODUCT ©2001 Silicon Storage Technology, Inc. Software Product ID Exit & ...
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... Address Wait T BE Block erased to FFH ( EQUENCE ODE 44 4 Mbit LPC Flash SST49LF040 Advance Information Sector-Erase Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: AAH Address: 5555H Write data: 55H ...
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... Suffix1 SST49LF0x0 - XXX - XX Valid combinations for SST49LF040 SST49LF040-33-4C-WH SST49LF040-33-4C-NH Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2001 Silicon Storage Technology, Inc. Suffix2 ...
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... R. x 30˚ MAX. .023 .030 .021 .013 .400 .032 BSC .026 .050 BSC .015 Min. .095 .075 .140 .125 (PLCC Mbit LPC Flash SST49LF040 Advance Information BOTTOM VIEW R. .530 .490 .032 .026 32-plcc-NH-ILL.2 S71213-00-000 11/01 562 ...
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... Mbit LPC Flash SST49LF040 Advance Information Pin # 1 Identifier 12.50 12.30 0.70 0.50 14.20 13.80 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. ...
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... Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2001 Silicon Storage Technology, Inc. www.SuperFlash.com or www.ssti.com 48 4 Mbit LPC Flash SST49LF040 Advance Information S71213-00-000 11/01 562 ...