74F646_04 FAIRCHILD [Fairchild Semiconductor], 74F646_04 Datasheet

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74F646_04

Manufacturer Part Number
74F646_04
Description
Octal Transceiver/Register with 3-STATE Outputs
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
© 2004 Fairchild Semiconductor Corporation
74F646SC
74F646MSA
74F646SPC
74F646
Octal Transceiver/Register with 3-STATE Outputs
General Description
These devices consist of bus transceiver circuits with
3-STATE, D-type flip-flops, and control circuitry arranged
for multiplexed transmission of data directly from the input
bus or from the internal registers. Data on the A or B bus
will be clocked into the registers as the appropriate clock
pin goes to a high logic level. Control G and direction pins
are provided to control the transceiver function. In the
transceiver mode, data present at the high impedance port
may be stored in either the A or the B register or in both.
The select controls can multiplex stored and real-time
(transparent mode) data. The direction control determines
which bus will receive data when the enable control G is
Active LOW. In the isolation mode (control G HIGH), A data
may be stored in the B register and/or B data may be
stored in the A register.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Order Number
Package Number
MSA24
IEEE/IEC
M24B
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
DS009580
Features
Connection Diagram
Independent registers for A and B buses
Multiplexed real-time and stored data
74F646 has non-inverting data paths
3-STATE outputs
300 mil slim DIP
Package Description
March 1988
Revised January 2004
www.fairchildsemi.com

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74F646_04 Summary of contents

Page 1

Octal Transceiver/Register with 3-STATE Outputs General Description These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on ...

Page 2

Unit Loading/Fan Out Pin Names Description A –A Data Register A Inputs 3-STATE Outputs B –B Data Register B Inputs 3-STATE Outputs CPAB, CPBA Clock Pulse Inputs SAB, SBA Select Inputs G Output Enable Input DIR ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 3) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...

Page 4

AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH t Clock to Bus PHL t Propagation Delay PLH t Bus to Bus PHL t Propagation Delay PLH t SBA or SAB ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 24-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number M24B Package Number MSA24 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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