mx25l3237d Macronix International Co., mx25l3237d Datasheet - Page 18

• Manufacturer Part Number: mx25l3237d
• Description: Serial Flash Memory
• Manufacturer: Macronix International Co.

P/N: PM1393
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write
Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR
instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as
shown in table 1). The WRSR also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write
Disable (SRWD) bit in accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0
(WIP) of the statur register. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is
entered.
The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register data
on SI-> CS# goes high. (see Figure 13)
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-
timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing,
and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
Table 6. Protection Modes
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
-
-
Note:
If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been
set. It is rejected to write the Status Register and not be executed.
Software protection
mode(SPM)
Hardware protection
mode (HPM)
When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change
the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software
protected mode (SPM).
When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD,
BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode
(SPM)
Mode
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
bits can be changed
The SRWD, BP0-BP3 of
status register bits cannot be
changed
Status register condition
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
WP# and SRWD bit status
18
WP#=0, SRWD bit=1
MX25L3237D
The protected area cannot
be program or erase.
The protected area cannot
be program or erase.
Memory
REV. 0.02, JUN. 13, 2008