mx25l3237d Macronix International Co., mx25l3237d Datasheet - Page 24

• Manufacturer Part Number: mx25l3237d
• Description: Serial Flash Memory
• Manufacturer: Macronix International Co.

P/N: PM1393
Table 7. ID Definitions
(19) Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit secured OTP mode. The additional 4K-bit secured OTP is
independent from main array, which may use to store unique serial number for system identifier. After entering the Secured
OTP mode, and then follow standard read or program, procedure to read out the data or update data. The Secured OTP
data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low-> sending ENSO instruction to enter Secured OTP mode
-> CS# goes high.
Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once security
OTP is lock down, only read related commands are valid.
(20) Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low-> sending EXSO instruction to exit Secured OTP mode->
CS# goes high.
(21) Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any
time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low-> send ing RDSCUR instruction -> Security Register data
out on SO-> CS# goes high.
The definition of the Security Register bits is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or not.
When it is "0", it indicates non- factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-
down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be
update any more. While it is in 4K-bit secured OTP mode, array access is not allowed.
Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP mode, "0"
indicates not in CP mode; "1" indicates in CP mode.
Command Type
RDID (JEDEC ID)
RES
REMS/REMS2/
REMS4
Manufacturer ID
Manufacturer ID
C2
C2
MX25L3237D
Memory type
Electronic ID
Device ID
5E
5E
5E
24
Memory Density
16
MX25L3237D
REV. 0.02, JUN. 13, 2008