mx25l3237d Macronix International Co., mx25l3237d Datasheet - Page 22

• Manufacturer Part Number: mx25l3237d
• Description: Serial Flash Memory
• Manufacturer: Macronix International Co.

P/N: PM1393
(14) 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before sending the
Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3, which can raise
programer performance and and the effectiveness of application of lower clock less than 20MHz. For system with faster
clock, the Quad page program cannot provide more actual favors, because the required internal page program time is far
more than the time data flows in. Therefore, we suggest that while executing this command (especially during sending
data), user can slow the clock speed down to 20MHz below. The other function descriptions are as same as standard page
program.
The sequence of issuing 4PP instruction is: CS# goes low-> sending 4PP instruction code-> 3-byte address on SIO[3:0]-
> at least 1-byte on data on SIO[3:0]-> CS# goes high. (see Figure 20)
(15) Continuously program mode (CP mode)
The CP mode may enhance program performance by automatically increasing address to the next higher address after
each byte data has been programmed.
The Continuously program (CP) instruction is for multiple byte program to Flash. A write Enable (WREN) instruction must
execute to set the Write Enable Latch(WEL) bit before sending the Continuously program (CP) instruction. CS# requires
to go high before CP instruction is executing. After CP instruction and address input, two bytes of data is input sequentially
from MSB(bit7) to LSB(bit0). The first byte data will be programmed to the initial address range with A0=0 and second
byte data with A0=1. If only one byte data is input, the CP mode will not process. If more than two bytes data are input,
the additional data will be ignored and only two byte data are valid. The CP program instruction will be ignored and not affect
the WEL bit if it is applied to a protected memory area. Any byte to be programmed should be in the erase state (FF) first.
It will not roll over during the CP mode, once the last unprotected address has been reached, the chip will exit CP mode
and reset write Enable Latch bit (WEL) as "0" and CP mode bit as "0". Please check the WIP bit status if it is not in write
progress before entering next valid instruction. During CP mode, the valid commands are CP command (AD hex), WRDI
command (04 hex), RDSR command (05 hex), and RDSCUR command (2B hex). And the WRDI command is valid after
completion of a CP programming cycle, which means the WIP bit=0.
The sequence of issuing CP instruction is : CS# high to low-> sending CP instruction code-> 3-byte address on SI-> Data
Byte on SI->CS# goes high to low-> sending CP instruction......-> last desired byte programmed or sending Write Disable
(WRDI) instruction to end CP mode-> sending RDSR instruction to verify if CP mode is ended. (see Figure 21 of CP mode
timing waveform)
Three methods to detect the completion of a program cycle during CP mode:
1) Software method-I: by checking WIP bit of Status Register to detect the completion of CP mode.
2) Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not.
3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a program
(16) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the
Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the
cycle during CP mode. The ESRY instruction must be executed before CP mode execution. Once it is enable in CP
mode, the CS# goes low will drive out the RY/BY# status on SO, "0" indicates busy stage, "1" indicates ready stage,
SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to disable the SO to output
RY/BY# and return to status register data output during CP mode. Please note that the ESRY/DSRY command are not
accepted unless the completion of CP mode.
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MX25L3237D
REV. 0.02, JUN. 13, 2008