mx25l3237d Macronix International Co., mx25l3237d Datasheet - Page 20

• Manufacturer Part Number: mx25l3237d
• Description: Serial Flash Memory
• Manufacturer: Macronix International Co.

MX25L3237D
(9) 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register
must be set to "1" before seding the 4READ instruction.The address is latched on rising edge of SCLK, and data of every
four bits(interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte
can be at any location. The address is automatically increased to the next higher address after each byte data is shifted
out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the
highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform
as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low
sending 4READ instruction
24-bit address interleave
on SIO3, SIO2, SIO1 & SIO0
6 dummy cycles
data out interleave on SIO3, SIO2, SIO1 & SIO0
to end 4READ
operation can use CS# to high at any time during data out (see Figure 17 for 4 x I/O Read Mode Timing Waveform).
Another sequence of issuing 4 READ instruction especially useful in random access is : CS# goes low
sending 4 READ
instruction
3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0
performance enhance toggling bit P[7:0]
4
dummy cycles
data out still CS# goes high
CS# goes low (reduce 4 Read instruction)
24-bit random access
address (see figure 18 for 4x I/O read enhance performance mode timing waveform).
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
(10) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any
4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending
the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The
CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction
will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS#
goes high. (see Figure 22)
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and
sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by
BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
(11) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-
byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction.
The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the
instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low -> sending BE instruction code-> 3-byte address on SI -> CS#
goes high. (see Figure 23)
P/N: PM1393
REV. 0.02, JUN. 13, 2008
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