vpx3224d ETC-unknow, vpx3224d Datasheet - Page 13

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

Micronas
PRELIMINARY DATA SHEET
2.3. Video Sync Processing
Fig. 2–10 shows a block diagram of the front-end sync
processing. To extract the sync information from the
video signal, a linear phase lowpass filter eliminates all
noise and video contents above 1 MHz. The sync is sep-
arated by a slicer; the sync phase is measured. The in-
ternal controller can select variable windows to improve
the noise immunity of the slicer. The phase comparator
measures the falling edge of sync, as well as the inte-
grated sync pulse.
The sync phase error is filtered by a phase-locked loop
that is computed by the FP. All timing in the front-end is
derived from a counter that is part of this PLL, and it thus
counts synchronously to the video signal.
A separate hardware block measures the signal back
porch and also allows gathering the maximum/minimum
of the video signal. This information is processed by the
FP and used for gain control and clamping.
For vertical sync separation, the sliced video signal is in-
tegrated. The FP uses the integrator value to derive ver-
tical sync and field information.
Frequency and phase characteristics of the analog vid-
eo signal are derived from PLL1. The results are fed to
the rest of the video processing system in the backend.
The resizer unit uses them for data interpolation and
orthogonalization. A separate timing block derives the
timing reference signals HREF and VREF from the hori-
zontal sync.
video
input
Fig. 2–10: Sync separation block diagram
lowpass
1 MHz &
sync
slicer
horizontal
sync
separation
clamp &
signal
measurement
phase
comparator
& lowpass
clamping
2.4. Macrovision Detection (version D4 only)
Video signals from Macrovision encoded VCR tapes are
decoded without loss of picture quality. However, it might
be necessary in some applications to detect the pres-
ence of Macrovision encoded video signals. This is pos-
sible by reading a set of I
0x170–0x179) in the video front-end.
Macrovision encoded video signals typically have AGC
pulses and pseudo sync pulses added during VBI. The
amplitude of the AGC pulses is modulated in time. The
Macrovision detection logic measures the VBI lines and
compares the signal against programmable thresholds.
The window in which the video lines are checked for Ma-
crovision pulses can be defined in terms of start and stop
line (e.g. 6–15 for NTSC).
front-end
timing
counter
color key FIFO_write
VPX 3225D, VPX 3224D
clock
synthesizer
syncs
front
sync
generator
PLL1
2
C registers (FP-RAM
front sync
skew
vblank
field
clock
H/V syncs
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