vpx3224d ETC-unknow, vpx3224d Datasheet - Page 7

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

Micronas
PRELIMINARY DATA SHEET
1.1. System Architecture
The block diagram (Fig. 1–1) illustrates the signal flow
through the VPX. A sampling stage performs 8-bit A/D
conversion, clamping, and AGC. The color decoder sep-
arates the luma and chroma signals, demodulates the
chroma, and filters the luminance. A sync slicer detects
the sync edge and computes the skew relative to the
sample clock. The video processing stage resizes the
YCbCr samples, adjusts the contrast and brightness,
and interpolates the chroma. The text slicer extracts
lines with text information and delivers decoded data
bytes to the video interface.
Note: The VPX 3225D and VPX 3224D are not register
compatible with the VPX 3220A, VPX 3216B, and
VPX 3214C family.
CVBS/Y
Fig. 1–1: Block diagram of the VPX 3224D, VPX 3225D
Chroma
SDA
SCL
Clock Gen.
DCO
I2C
ADC
ADC
JTAG
(VPX 3225D only)
Sync Processing
Video Decoder
Text Slicer
Luma Filter
Chroma
Demodulator
Line Store
C
b
Y
C
VPX 3225D, VPX 3224D
r
C
b
Y
C
r
HREF
VREF
FIELD
A[7:0]
OEQ
B[7:0]
PIXCLK
LLC
VACT
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