vpx3224d ETC-unknow, vpx3224d Datasheet - Page 56

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

56
VPX 3225D, VPX 3224D
4.3.5. Characteristics, Control Bus Interface
(Timing diagram see Fig. 5–3 on page 61)
4.3.6. Characteristics, JTAG Interface (Test Access Port TAP)
(Timing diagram see Fig. 5–5 on page 63)
Symbol
V
t
t
t
f
1)
IMOL1
IMOL2
F
SCL
Symbol
F
F
F
V
Test Access Port (TAP), see timing diagram (Fig. 5–5 on page 63)
t
t
t
t
t
Boundary-Scan Test, Characteristics of all IO pins which are connected to the boundary scan register chain
t
t
t
t
t
IMOL
S-TAP
H-TAP
D-TAP
ON-TAP
OFF-TAP
S-PINS
H-PINS
D-PINS
ON-PINS
OFF-PINS
The maximum clock frequency of the I2C interface is limited to 100 kHz while the IC is working in the low power mode.
RES-TAP
CYCL-TAP
H-TAP
L-TAP
Parameter
Output Low Voltage
I
Falling Edge of Clock SCL
I
fore Rising Edge of Clock SCL
Signal Fall Time
Clock Frequency
2
2
Parameter
JTAG Cycle Time
TCK High Time
TCK Low Time
Minimum supply voltage to initiate an
internal reset of the JTAG-TAP generated
by a voltage supply supervision circuit
TMS, TDI Setup Time
TMS, TDI Hold Time
TCK to TDO Propagation Delay
for Valid Data
TDO Turn-on Delay
TDO Turn-off Delay
Input Signals Setup Time at CAPTURE-DR
Input Signals Hold Time at CAPTURE-DR
TCK to Output Signals,
Delay for Valid Data
Turn-on Delay
Turn-off Delay
C-Data Output Hold Time after
C-Data Output Setup Time be-
1)
Pin
Name
SDA,
SCL
SDA
SDA
SDA,
SCL
SCL
Min.
–
15
100
–
0
Min.
100
50
50
3.5
12
12
10
10
Typ.
–
–
–
Typ.
Max.
0.4
0.6
300
100
1000
Max.
50
45
45
50
20
20
Unit
V
V
ns
ns
ns
kHz
kHz
Unit
ns
ns
ns
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PRELIMINARY DATA SHEET
Test Conditions
I
I
f
C
R
low power mode
normal operating condition
l
l
SCL
Test Conditions
VDD pin
= 3 mA
= 6 mA
L
PU
= 400 pF,
= 1 MHz, VDD = 5 V
= 4,7 k
Micronas