vpx3224d ETC-unknow, vpx3224d Datasheet - Page 83

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

Micronas
PRELIMINARY DATA SHEET
7. Application Notes
7.1. Differences between VPX 3220A and VPX 322xD
The following items indicate the differences between the
VPX 322xD and the VPX 3220A:
Internal
– The control registers (I
– VPX 322xD incorporates a text slicer. Furthermore,
– VPX 322xD does not support RGB and compressed
– The VPX 322xD does not provide an asynchronous
– The VPX 322xD does not provide a video data rate of
– The VPX 322xD has an implemented low power
External
– Power-up Default Selection
– The VPX 322xD does not use the internal I
– The VPX 322xD supports an 8-bit programmable out-
– The VPX 322xD provides a HREF signal with a fixed
icant changes.
raw ADC data is supported (sampling frequency of
20.25 MHz/8 bit, output data rate 13.5 MHz/16 bit).
video data output formats. The VPX 322xD supports
ITU-R601 and ITU-R656.
output mode, PIXCLK functions as an output only. The
VPX 322xD supports half-clock data rate (6.75 MHz).
20.25 MHz at the output interface.
mode.
power-up initialization. Resultingly, the I
will not be locked during that period.
put port if the device uses only A[7:0] for video data
output.
low period, whereas the width of the high period will
vary while the video input signal varies.
Selection
I
address
wake-up default
Pads tristate/
active
2
C device
2
C and FP-RAM) contain signif-
VPX 3220A
PREF
PIXCLK
VPX 322xD
OE
FIELD
2
C interface
2
C bus for
7.2. Impact to Signal to Noise Ratio
Fig. 7–1 shows the impact of the variation of the power
supply with respect to the SNR of the ADCs. The noise
due to the digital output interface leads to an impact of
the analog performance of the analog ADCs. Application
engineers should minimize load capacitances and driver
strength of the output signals.
Fig. 7–1: Dependency between SNR and
Power Supply
Note: Both ADCs are working and routed to A[7:0], and
B[7:0]. All interfaces are working with maximum driver
strength bandwidth measurement is performed up to 5
MHz.
7.3. Control Interface
7.3.1. Symbols
<
>
aa
dd
7.3.2. Write Data into I
<86 f2 dd>
7.3.3. Read Data from I
<86 00 <87 dd>
7.3.4. Write Data into FP Register
<86 35 <87 dd>
<86 37 aa aa>
<86 35 <87 dd>
<86 38 dd dd>
7.3.5. Read Data from FP Register
<86 35 <87 dd>
<86 36 aa aa>
<86 35 <87 dd>
<86 38 <87 dd dd> read data from FP register
45
44
43
42
41
40
39
38
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Start Condition
Stop Condition
(Sub-)Address Byte
Data Byte
VPX 3225D, VPX 3224D
PVDD [V]
write to register OENA
read Manufacture ID
poll busy bit[2] until it is cleared
write FP register write address
poll busy bit[2] until it is cleared
write data into FP register
poll busy bit[2] until it is cleared
write FP register read address
poll busy bit[2] until it is cleared
2
2
C Register
C Register
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