vpx3224d ETC-unknow, vpx3224d Datasheet - Page 44

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

44
VPX 3225D, VPX 3224D
2.17. Enable/Disable of Output Signals
In order to enable the output pins of the VPX to achieve
the high impedance/tristate mode, various controls have
been implemented. The following paragraphs give an
overview of the different tristate modes of the output sig-
nals. It is valid for all output pins, except the XTAL2
(which is the oscillator output) and the VRT pin (which is
an analog reference voltage).
BS (Boundary Scan) Mode:
The tristate control by the test access port TAP for
boundary scan has the highest priority. Even if the TAP-
controller is in the EXTEST or CLAMP mode, the tristate
behavior is only defined by the state of the different
boundary scan registers for enable control. If the TAP
controller is in HIGHZ mode, then all output pins are in
tristate mode independently of the state of the different
boundary scan registers for enable control.
RESET State:
If the TAP-controller is not in the EXTEST mode, then the
RESET-state defines the state of all digital outputs. The
only exception is made for the data output of the bound-
ary scan interface TDO. If the circuit is in reset condition
(RES = 0), then all output interfaces are in tristate mode.
Table 2–17: Output driver configuration
Remark: EXTEST mode is an instruction conforming to the standard for Boundary Scan Test IEEE 1149.1 – 1990
EXTEST
active
inactive
inactive
inactive
inactive
RESET
–
active
inactive
inactive
inactive
I
–
–
= 0
= 1
= 1
2
C
OE#
–
–
–
= 0
= 1
Driver Stages
Output driver stages are defined by the state of the different
boundary scan enable registers.
Output drivers are in high impedance mode.
Output drivers are in high impedance mode. PIXCLK is working.
Output drivers HREF, VREF, FIELD, VACT, LLC, are working.
Outputs A[7:0] and B[7:0] are working
Output drivers HREF, VREF, FIELD, VACT, LLC, are working.
Output drivers of A[7:0] and B[7:0] are in high impedance mode.
I
The tristate condition of groups of signals can also be
controlled by setting the I
is neither in EXTEST mode nor RESET state, then the
I
tate condition or not (see “I
end”).
Output Enable Input OE:
The output enable signal OE only effects the video out-
put ports. If the previous three conditions do not cause
the output drivers to go into high impedance mode, then
the OE signal defines the driving conditions of the video
data ports.
The OE pin function can be disabled via I
0xF2 [oeq_dis]. The OE signal will either directly con-
nect the output drivers or it will be latched internally with
the LLC signal depending on I
Additionally, a delay of 1 LLC clock cycle can be enabled
with I
2
2
C Control:
C-Register 0xF2 defines whether the output is in tris-
2
C register 0xF2 [oeqdel].
PRELIMINARY DATA SHEET
2
C-Register 0xF2. If the circuit
2
2
C-Registers VPX Back-
C register 0xF2 [latoeq].
2
C register
Micronas