vpx3224d ETC-unknow, vpx3224d Datasheet - Page 57

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

Micronas
PRELIMINARY DATA SHEET
4.3.7. Characteristics, Digital Inputs/Outputs
4.3.8. Clock Signals PIXCLK, LLC, and LLC2
The following timing specifications refer to the timing diagrams of section 5.7.1. on page 64.
Symbol
Digital Input Pins TMS, TDI, TCK, RES, OE, SCL, SDA
C
I
I
I
Digital Output pins A[7:0], B[7:0], HREF, VREF, FIELD, VACT, LLC, PIXCLK, TDO
C
V
V
V
I
A special VDD, VSS supply is used only to support the digital output pins. This means, inherently, that in case of tri-state conditions,
external sources should not drive these signals above the voltage PVDD which supplies the output pins.
Symbol
t
F
t
F
t
F
t
t
t
t
I
I
PD
O
LLC
LLC2
PIXCLK
HCLK1
DCLK1
HCLK2
DCLK2
OL
OL
OH
IN
O
LLC
LLC2
PIXCLK
Parameter
Input Capacitance
Input Leakage Current
Input Pins TCK, RES, OE, SCL, SDA
Input Leakage Current
Input Pins with Pull-ups: TDI and TMS
Pull-down Current at Pin FIELD
during RES = 0 for Default Selection
High-Impedance Output Capacitance
Output Voltage LOW
(all digital output pins except SDA, SCL)
Output Voltage LOW
(only SDA, SCL)
Output Voltage HIGH
(all digital output pins except SDA, SCL)
Output Leakage Current
Parameter
LLC Cycle Time
LLC Duty Cycle F
LLC2 Cycle Time
LLC2 Duty Cycle F
PIXCLK Cycle Time
PIXCLK Duty Cycle F
Output Signal Hold Time for LLC2
Propagation Delay for LLC2
Output Signal Hold Time for PIXCLK
Propagation Delay for PIXCLK
H
H
/ (F
/ (F
H
L +
/ (F
L +
F
L +
F
H
H
)
F
)
H
)
Min.
see section 4.3.2.
2.4
Min.
0
10
Typ.
5
–25
5
–
Typ.
37
50
74
50
74
50
VPX 3225D, VPX 3224D
Max.
8
–1
+1
–55
+1
8
0.6
0.4
0.6
PVDD
–1
+1
Max.
10
18
Unit
pF
mA
mA
pF
V
V
V
V
mA
mA
Unit
ns
%
ns
%
ns
%
ns
ns
ns
ns
Test Conditions
V
V
V
V
I
I
while IC remains in low
power mode
V
V
Test Conditions
l
l
I
I
I
I
I
I
= 3 mA
= 6 mA
= V
= V
= V
V
V
V
DD
DD
DD
SS
SS
SS
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