vpx3224d ETC-unknow, vpx3224d Datasheet - Page 39

• Manufacturer Part Number: vpx3224d
• Description: Video Pixel Decoders
• Manufacturer: ETC-unknow

Micronas
PRELIMINARY DATA SHEET
Tristate Cell
Each group of output signals, which are tristatable, is
controlled by a boundary scan cell (output cell type).
This allows either the normal system signal or the
scanned signal to control the tristate control. In the VPX,
there are four such tristate control cells which control
groups of output signals (see section “Output Driver Tris-
tate Control” for further information).
Bidirect Cell
The bidirect cell is comprised of an input cell and a tris-
tate cell as described in the IEEE standard. The signal
PIXCLK is a bidirectional signal.
2.16.2.4. Bypass Register
This register provides a minimal path between TDI and
TDO. This is required for complicated boards where
many chips may be connected in serial.
2.16.2.5. Device Identification Register
This is an optional 32-bit register which contains the
Micronas identification code (JEDEC controlled), part
and revision number. This is useful in providing the tes-
ter with assurance that the correct part and revision are
inserted into a PCB.
2.16.2.6. Master Mode Data Register
This is an optional register used to control an 8-bit test
register in the chip. This register supports shift and up-
date. No capture is supported. This was done so the last
word can be shifted out for verification.
2.16.3. Exception to IEEE 1149.1
There is one exception to IEEE 1149.1. The exception
is to paragraphs 3.1.1.c., 3.5.1.b, and 5.2.1.d (TEST-
LOGIC-RESET state). Because of pin limitations on the
chip, a pin is shared for two functions. When the circuit
is in the TEST-LOGIC-RESET state, the LLC2 signal is
driven out the TDO/LLC2 pin. When the circuit leaves
the TEST-LOGIC-RESET state, the TDO signal is driven
on this line. As long as the circuit is not in the TEST-LOG-
IC-RESET state, all the rules for application of the TDO
signal adhere to the IEEE1149.1 spec.
Since the VPX uses the JTAG function as a boundary-
scan tool, the VPX does not sacrifice test of this pin since
it is verified by exercising JTAG function. The designer
of the PCB must make careful note of this fact, since he
will not be able to scan into chips receiving the LLC2 sig-
nal via the VPX. The PCB designer may want to put this
chip at the end of the chain or bring the VPX TDO out
separately and not have it feed another chip in a chain.
2.16.4. IEEE 1149.1-1990 Spec Adherence
This section defines the details of the IEEE1149.1 de-
sign for the VPX. It describes the function as outlined by
IEEE1149.1, section 12.3.1. The section of that docu-
ment is referenced in the description of each function.
2.16.4.1. Instruction Register
(Section 12.3.1.b.i of IEEE 1149.1-1990)
The instruction register is three bits long. No parity bit is
included. The pattern loaded in the instruction register
during CAPTURE-IR is binary “101” (MSB to LSB). The
two LSBs are defined by the spec to be “01” (bit 1 and
bit 0) while the MSB (bit 2) is set to “1”.
2.16.4.2. Public Instructions
(Section 12.3.1.b.ii of IEEE 1149.1-1990)
A list of the public instructions is as follows:
The EXTEST and SAMPLE/PRELOAD instructions
both apply the boundary scan chain to the serial path.
The ID CODE instruction applies the ID register to the
serial chain. The BYPASS, the HIGHZ, and the CLAMP
instructions apply the bypass register to the serial chain.
The MASTER MODE instruction is a test data instruction
for public use. It provides the ability to control an 8-bit
test register in the chip.
Instruction
EXTEST
SAMPLE/PRELOAD
ID CODE
MASTER MODE
HIGHZ
CLAMP
BYPASS
VPX 3225D, VPX 3224D
Code (MSB to LSB)
000
001
010
011
100
110
100 – 111
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