act7000asc Aeroflex Circuit Technology, act7000asc Datasheet - Page 14

• Manufacturer Part Number: act7000asc
• Description: Standard Products Act7000asc 64-bit Superscaler Microprocessor
• Manufacturer: Aeroflex Circuit Technology

Performance Counters
the Performance Counter feature has been added to
improve the observability and controllability of the
processor thereby easing system debug and, especially in
the case of the performance counters, easing system tuning.
two new CP0 registers, PerfCount and PerfControl. The
PerfCount register is a 32-bit writable counter which
causes an interrupt when bit 31 is set. The PerfControl
register is a 32-bit register containing a five bit field which
selects one of twenty-two event types as well as a handful
of bits which control the overall counting function. Note
that only one event type can be counted at a time and that
counting can occur for user code, kernel code, or both. The
event types and control bits are listed in Table 10.
PerfControl
SysClock
Like the Test/Break-point capability described above,
The Performance Counter feature is implemented using
ValidOut*
Release*
SysCmd
SCD7000A Rev B
ValidIn*
RdRdy*
WrRdy*
Table 10 – Performance Counter Control
Field
SysAD
4..0
Event Type
00: Clock cycles
01: Total instructions issued
02: Floating-point instructions issued
03: Integer instructions issued
04: Load instructions issued
05: Store instructions issued
06: Dual issued pairs
07: Branch prefetches
08: External Cache Misses
09: Stall cycles
0A: Secondary cache misses
0B: Instruction cache misses
0C: Data cache misses
0D: Data TLB misses
0E: Instruction TLB misses
0F: Joint TLB instruction misses
10: Joint TLB data misses
11: Branches taken
Addr
Write
Description
NData NData
Data0 Data1
Figure 8 – Processor Block Write
14
interrupts are enabled in the Status register, IE=1, and
Interrupt Mask bit 13 (IM[13]) of the coprocessor 0
interrupt control register is not set.
Table 10 – Performance Counter Control (cont)
NData NEOD
NData
PerfControl
Data2 Data3
The performance counter interrupt will only occur when
Since the performance counter can be set up to count
4.0 con’t
31..11
Field
7..5
10
8
9
12: Branches issued
13: Secondary cache writebacks
14: Primary cache writebacks
15: Dcache miss stall cycles (cycles
16: Cache misses
17: FP possible exception cycles
18: Slip Cycles due to multiplier busy
19: Coprocessor 0 slip cycles
1A: Slip cycles due to pending
1B: Write buffer full stall cycles
1C: Cache instruction stall cycles
1D: Multiplier stall cycles
1E: Stall cycles due to pending
Reserved (must be zero)
Count in Kernel Mode
0: Disable
1: Enable
Count in User Mode
0: Disable
1: Enable
Count Enable
0: Disable
1: Enable
Reserved (must be zero)
where both cache miss tokens
taken and a third address is
requested)
non-blockingloads
non-blocking loads - stall start of
exception
Description