act7000asc Aeroflex Circuit Technology, act7000asc Datasheet - Page 23

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act7000asc

Manufacturer Part Number
act7000asc
Description
Standard Products Act7000asc 64-bit Superscaler Microprocessor
Manufacturer
Aeroflex Circuit Technology
Datasheet
Microprocessor see the latest PMCS datasheet and users guide.
The following is a list of control, data, clock, interrupt, and miscellaneous pins of the ACT 7000ASC.
For additional Detail Information regarding the operation of the PMC-Sierra RM7000A, 64-Bit Superscalar
JTAG interface:
JTDI
JTCK
JTDO
JTMS
Initialization Interface:
BigEndian
VccOK
ColdReset*
Reset*
ModeClock
ModeIn
SCD7000A Rev B
Pin Name
Input
Input
Output
Input
Input
Input
Input
Input
Output
Input
Type
JTAG data in
JTAG serial data in.
JTAG clock input
JTAG serial clock input.
JTAG data out
JTAG serial data out.
JTAG command
JTAG command signal, signals that the incoming serial data is command data.
Big Endian / Little Endian Control
Allows the system to change the processor addressing mode without rewriting
the mode ROM.
Vcc is OK
When asserted, this signal indicates to the ACT-7000ASC that the V
supply has been above the recommended value for more than 100 milliseconds
and will remain stable. The assertion of VccOK initiates the reading of the
boot-time mode control serial stream.
Cold Reset
This signal must be asserted for a power on reset or a cold reset. ColdReset
must be de-asserted synchronously with SysClock.
Reset
This signal must be asserted for any reset sequence. It may be asserted
synchronously or asynchronously for a cold reset, or synchronously to initiate a
warm reset. Reset must be de-asserted synchronously with SysClock.
Boot Mode Clock
Serial boot-mode data clock output at the system clock frequency divided by two
hundred and fifty six.
Boot Mode Data In
Serial boot-mode data input.
Pin Descriptions (cont)
23
Description
CC
I
NT
power

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