act7000asc Aeroflex Circuit Technology, act7000asc Datasheet - Page 22

• Manufacturer Part Number: act7000asc
• Description: Standard Products Act7000asc 64-bit Superscaler Microprocessor
• Manufacturer: Aeroflex Circuit Technology

The following is a list of control, data, clock, interrupt, and miscellaneous pins of the ACT 7000ASC.
System interface:
ExtRqst*
Release*
RdRdy*
WrRdy*
ValidIn*
ValidOut*
SysAD(63:0)
SysADC(7:0)
SysCmd(8:0)
SysCmdP
Clock/Control interface:
SysClock
VccP
VssP
Interrupt Interface
Int*(5:0)
NMI*
SCD7000A Rev B
Pin Name
Input
Output
Input
Input
Input
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input
Input
Input
Input
Input
Type
External request
Signals that the system interface is submitting an external request.
Release interface
Signals that the processor is releasing the system interface to slave state
Read Ready
Signals that an external agent can now accept a processor read.
Write Ready
Signals that an external agent can now accept a processor write request.
Valid Input
Signals that an external agent is now driving a valid address or data on the
SysAD bus and a valid command or data identifier on the SysCmd bus.
Valid output
Signals that the processor is now driving a valid address or data on the SysAD
bus and a valid command or data identifier on the SysCmd bus.
System address/data bus
A 64-bit address and data bus for communication between the processor and an
external agent.
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data cycles.
A 9-bit bus for command and data identifier transmission between the processor
and an external agent.
System Command/Data Identifier Bus Parity
For the RM7000A, unused on input and zero on output.
System clock
Master clock input used as the system interface reference clock. All output
timings are relative to this input clock. Pipeline operation frequency is derived by
multiplying this clock up by the factor selected during boot initialization
Vcc for PLL
Quiet VccInt for the internal phase locked loop. Must be connected to VccInt.
See Figure 10 for additional PPL filtering information.
Vss for PLL
Quiet Vss for the internal phase locked loop. Must be connected to Vss.
See Figure 10 for additional PPL filtering information.
Interrupt
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt
register.
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 15 of the interrupt register (bit 6 in R5000
compatibility mode).
System command/data identifier bus
Pin Descriptions
22
Description