act7000asc Aeroflex Circuit Technology, act7000asc Datasheet - Page 8

• Manufacturer Part Number: act7000asc
• Description: Standard Products Act7000asc 64-bit Superscaler Microprocessor
• Manufacturer: Aeroflex Circuit Technology

addressing, the virtual address space layout is an upward
compatible extension of the 32-bit virtual address space
layout.
Joint TLB
ACT 7000ASC uses a large, fully associative TLB that
maps virtual pages to their corresponding physical
addresses. As indicated by its name, the joint TLB (JTLB)
is used for both instruction and data translations. The JTLB
is organized as pairs of even/odd entries, and maps a virtual
address and address space identifier into the large, 64GB
physical address space. By default, the JTLB is configured
as 48 pairs of even/odd entries. The 64 even/odd entry
optional configuration is set at boot time.
amount
characteristics of various memory regions. First, the page
size can be configured, on a per-entry basis, to use page
sizes in the range of 4KB to 16MB (in 4X multiples). A
0xFFFFFFFF Kernel virtual address space
0xE0000000
0xDFFFFFFF Supervisor virtual address space
0xC0000000
0xBFFFFFFF Uncached kernel physical address space
0xA0000000
0x9FFFFFFF Cached kernel physical address space
0x80000000
0x7FFFFFFF User virtual address space
0x00000000
When the ACT 7000ASC is configured for 64-bit
For fast virtual-to-physical address translation, the
Two mechanisms are provided to assist in controlling the
Figure 5 – Kernel Mode Virtual Addressing
SCD7000A Rev B
of
mapped
(kseg3)
Mapped, 0.5GB
(ksseg)
Mapped, 0.5GB
(kseg1)
Unmapped, 0.5GB
(kseg0)
(kuseg)
Mapped, 2.0GB
Unmapped, 0.5GB
(32-bit mode)
space,
and
the
replacement
8
CP0 register, PageMask, is loaded with the desired page
size of a mapping, and that size is stored into the TLB along
with the virtual address when a new entry is written. Thus,
operating systems can create special purpose maps; for
example, a typical frame buffer can be memory mapped
using only one TLB entry.
algorithm when a TLB miss occurs. The ACT 7000ASC
provides a random replacement algorithm to select a TLB
entry to be written with a new mapping; however, the
processor also provides a mechanism whereby a system
specific number of mappings can be locked into the TLB,
thereby avoiding random replacement. This mechanism
allows the operating system to guarantee that certain pages
are always mapped for performance reasons and for
deadlock avoidance. This mechanism also facilitates the
design of real-time systems by allowing deterministic
access to critical software.
cache coherency protocol for each page. Specifically, each
page has attribute bits to determine whether the coherency
algorithm is: uncached, write-back, write-through with
write-allocate,
write-back with secondary bypass. Note that both of the
write-through protocols bypass the secondary cache since it
does not support writes of less than a complete cache line.
ACT 7000ASC
write-through depending
write-through modes support the same efficient frame
buffer handling as the RM5200 Family, R4700 and R5000.
Instruction TLB
(ITLB) to minimize contention for the JTLB, to eliminate
the critical path of translating through a large associative
array, and to save power. Each ITLB entry maps a 4KB
page. The ITLB improves performance by allowing
instruction address translation to occur in parallel with data
address translation. When a miss occurs on an instruction
address translation by the ITLB, the least-recently used
ITLB entry is filled from the JTLB. The operation of the
ITLB is completely transparent to the user.
Data TLB
the same reasons cited above for the ITLB. Each DTLB
entry maps a 4KB page. The DTLB improves performance
by allowing data address translation to occur in parallel
with instruction address translation. When a miss occurs on
a data address translation by the DTLB, the DTLB is filled
from the JTLB. The DTLB refill is pseudo-LRU: the least
recently used entry of the least recently used pair of entries
is filled. The operation of the DTLB is completely
transparent to the user.
Cache Memory
pipeline full and operating efficiently, the ACT 7000ASC
has integrated primary instruction and data caches with
single cycle access as well as a large unified secondary
The second mechanism controls the replacement
The JTLB also contains information that controls the
These protocols are used for both code and data on the
The ACT 7000ASC uses a 4-entry instruction TLB
The ACT 7000ASC uses a 4-entry data TLB (DTLB) for
In order to keep the ACT 7000ASC’s superscalar
write-through
with
data
on
without
using
the
application.
write-back
write-allocate,
The
or