em65570sagh ELAN Microelectronics Corp, em65570sagh Datasheet - Page 59

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em65570sagh

Manufacturer Part Number
em65570sagh
Description
68com/98seg 65k Color Stn Lcd Drivers
Manufacturer
ELAN Microelectronics Corp
Datasheet
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
D7
0
Register address
8.2 Control Registers Functions
D6
0
D5
0
(At the time of reset: {AX3, AX2, AX1, AX0}= 0H, read address: 0H)
(At the time of reset: {AX7, AX6, AX5, AX4}= 0H, read address: 1H)
The EM65570S has many control registers. In case of control register access, upper
nibble of data bus (D7~D4) represent register address, lower nibble of data bus
(D3~D0) represent data. The access example is shown in the following. The Pins
(CSB, RS, RDB, WRB) setting is for 80-family MPU interface. Only the setting of
terminal (RDB, WRB) is different, when it is accessed by the 68-fanily MPU.
(Example) X Address
In the writing to the control register, it is used directly as addressing D7~D4 of the data
bus. In case of register read, first set RA register for specific register address, next can
read specific register. Therefore, it is need 2-step for register read. Then, specific
register output to D3~D0 of data bus. Except D3~D0 of data bus are all “H”. Prohibit
access to undefined register address area. When RS is “L”, all read/write operations
are accessed to display RAM. Then data bus doesn’t include register address. In case
of write, D3~D0 data is written to the register designated at D7~D4 in rising edge of the
WRB signal. In case of read, register can output to data bus is RDB active period.
Control register and display RAM are the equal access timing.
8.2.1 X Address Register (AX)
The AX register set to X-direction address of display RAM. In data setting, lower place
and upper place are divided with 4-bit and 4-bit respectively. 00H to 61H are applicable
to the values for AX7 to AX0, and 62H to FFH are not permitted.
8.2.2 Y Address Register (AY)
(At the time of reset: {AY3, AY2, AY1, AY0}=0H, read address: 2H)
D7
D7
D7
0
0
0
D4
0
D6
D6
D6
0
0
0
AX3 AX2 AX1 AX0
D3
D5
D5
D5
1
0
0
D4
0
D2
D4
D4
1
0
Data
AY3 AY2 AY1 AY0
D3
AX3 AX2 AX1 AX0
AX7 AX6 AX5 AX4
D3
D3
D1
D2
D2
D2
D0
D1
D1
D1
D0
D0
D0
CSB
0
68COM/98SEG 65K Color STN LCD Drivers
Pins setting
RS
CSB
CSB RS
CSB
1
0
0
0
RDB WRB
RS
RS RDB WRB RE2 RE1 RE0
1
1
1
1
RDB WRB RE2 RE1 RE0
RDB WRB RE2 RE1 RE0
1
1
1
0
0
0
0
RE2
0
Register Bank
0
0
0
EM65570S
RE1
0
0
0
0
RE0
0
x 53
0
0
0

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