h8s-2138 Renesas Electronics Corporation., h8s-2138 Datasheet - Page 971

• Manufacturer Part Number: h8s-2138
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

SSR1—Serial Status Register 1
SSR2—Serial Status Register 2
SSR0—Serial Status Register 0
Bit
Initial value
Read/Write
Transmit data register empty
0 [Clearing conditions]
1 [Setting conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written in TDR
R/(W) *
TDRE
7
1
R/(W) *
RDRF
Receive data register full
6
0
0 [Clearing conditions]
1 [Setting condition]
• When 0 is written in RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
When serial reception ends normally and receive data is transferred from RSR to RDR
R/(W) *
ORER
Overrun error
0 [Clearing condition]
1 [Setting condition]
5
0
When the next serial reception is completed while RDRF = 1
When 0 is written in ORER after reading ORER = 1
Framing error
0 [Clearing condition]
1 [Setting condition]
When 0 is written in FER after reading FER = 1
When the SCI checks the stop bit at the end of the receive data
when reception ends, and the stop bit is 0
R/(W) *
FER
4
0
Parity error
0 [Clearing condition]
1 [Setting condition]
When 0 is written in PER after reading PER = 1
When, in reception, the number of 1 bits in the receive
data plus the parity bit does not match the parity setting
(even or odd) specified by the O/E bit in SMR
Rev. 4.00 Jun 06, 2006 page 917 of 1004
R/(W) *
Transmit end
H'FF8C
H'FFA4
H'FFDC
PER
0 [Clearing conditions]
1 [Setting conditions]
3
0
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
writes data to TDR
a 1-byte serial transmit character
Appendix B Internal I/O Registers
Note: * Only 0 can be written, to clear the flag.
TEND
Multiprocessor bit
R
2
1
0 [Clearing condition]
1 [Setting condition]
When data with a 0 multiprocessor
bit is received
When data with a 1 multiprocessor
bit is received
Multiprocessor bit transfer
0 Data with a 0 multi-processor
1 Data with a 1 multi-processor
bit is transmitted
bit is transmitted
MPB
R
1
0
REJ09B0301-0400
MPBT
R/W
0
0
SCI1
SCI2
SCI0