PF38F5070M0Y0T0 NUMONYX [Numonyx B.V], PF38F5070M0Y0T0 Datasheet - Page 43

• Manufacturer Part Number: PF38F5070M0Y0T0
• Description: Numonyx StrataFlash Wireless Memory
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ StrataFlash
Table 19: Read Configuration Register Description (Sheet 2 of 2)
10.3.1
10.3.2
November 2007
Order Number: 313295-04
13:11
10
9
8
7
6
5:4
3
2:0
Latency Count (LC[2:0])
Wait Polarity (WP)
Data Hold (DH)
Wait Delay (WD)
Burst Sequence (BS)
Clock Edge (CE)
Reserved (R)
Burst Wrap (BW)
Burst Length (BL[2:0])
Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous read-mode
operation for the device. When the RM bit is set, asynchronous read mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
Latency Count
The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse
from the rising edge of ADV# or from the first valid clock edge after ADV# is asserted
before the WAIT signal indicates valid data is present on the device data signals
AD[15:0]. The input clock frequency determines this value.
output latency from ADV#-asserted for different settings of LC[2:0]. The Latency Count
does not affect when data becomes available on the data signals. Valid data is driven
onto the data bus, with respect to a valid clock edge, as soon as possible after the
asynchronous access time is satisfied (or another word after it is sensed). In this way,
the data “flows-through” on the first access, with respect to an active clock edge. The
data continues to be available on the data bus until the latency period is over. The flow-
through behavior only applies to the first access of any bus cycle. All subsequent data
is driven on valid clock edges following the first access latency period.
During synchronous burst a Latency Count setting of Code 5 will cause 1 WAIT state
(Code 6 will cause 2 WAIT states, and Code 7 will cause 3 WAIT states) after every four
words, regardless of whether a 16-word boundary is crossed. If CR.[9] (Data Hold) bit
is set (data hold of two clocks) this WAIT condition will not occur because enough
clocks elapse during each burst cycle to eliminate subsequent WAIT states.
®
Wireless Memory (L18 AD-Mux)
010 =Code 2
011 =Code 3
100 =Code 4
101 =Code 5
110 =Code 6
111 =Code 7(default)
(Other bit settings are reserved)
0 =WAIT signal is active low
1 =WAIT signal is active high (default)
0 =Data held for a 1-clock data cycle
1 =Data held for a 2-clock data cycle (default)
0 =WAIT de-asserted with valid data
1 =WAIT de-asserted one data cycle before valid data (default)
0 =Reserved
1 =Linear (default)
0 = Falling edge
1 = Rising edge (default)
Reserved bits should be cleared (0)
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
(Other bit settings are reserved)
Figure 16
shows the data
Datasheet
43