PF38F5070M0Y0T0 NUMONYX [Numonyx B.V], PF38F5070M0Y0T0 Datasheet - Page 45

• Manufacturer Part Number: PF38F5070M0Y0T0
• Description: Numonyx StrataFlash Wireless Memory
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ StrataFlash
Figure 17: Example Latency Count Setting with Flow- through feature
Note:
10.3.3
10.3.3.1
Table 22: WAIT Summary Table
November 2007
Order Number: 313295-04
A/DQ
CE# = V
CE# = V
OE# = V
OE# = V
Synchronous Array and Non-array Reads
All Asynchronous Read and all Write
ADV#
A
CE#
MAX-16
CLK
15-0
The waveform above illustrates the Latency Count of 4 with Flow-through feature. The Flow-through feature will be shown
only when the initial access time is one clock less than the LC setting.
IH
IL
IH
IL
WAIT Polarity
The WAIT Polarity bit (WP), RCR[10] determines the asserted level (V
WAIT. When WP is set, WAIT is asserted-high (default). When WP is cleared, WAIT is
asserted-low. WAIT changes state on valid clock edges during active bus cycles (CE#
asserted, OE# asserted and RST# deasserted).
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(CR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works
correctly only on the first data access.
When the device is operating in asynchronous single word read mode, WAIT is set to an
“de-asserted” state as determined by CR[10]. See
page
Valid Address
t
45, and
®
CONDITION
ADD
Wireless Memory (L18 AD-Mux)
Code 4
Figure 6, “Asynchronous Single-Word Read Timing” on page
1st
R2
High Z
2nd
High-Z
Driven
De-asserted
Active
Active
De-asserted
3rd
Table 22, “WAIT Summary Table” on
t
CHQV
4th
WAIT
Output
Valid
5th
OH
t
DATA
or V
25.
OL
Output
) of
Datasheet
Valid
6th
45