LTC2414 LINER [Linear Technology], LTC2414 Datasheet - Page 24

• Manufacturer Part Number: LTC2414
• Description: 8-/16-Channel 24-Bit No Latency TM ADCs
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC2414/LTC2418
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data input/
output cycle begins on the first rising edge of SCK and
ends after the 32nd rising edge. The input data is then
shifted in via the SDI pin on the rising edge of SCK
(including the first rising edge) and the output data is
shifted out of the SDO pin on each falling edge of SCK.
The internally generated serial clock is output to the SCK
pin. This signal may be used to shift the conversion result
into external circuitry. EOC can be latched on the first
rising edge of SCK and the last bit of the conversion result
can be latched on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1) indicating a
new conversion is in progress. SCK remains HIGH during
the conversion.
PRESERVING THE CONVERTER ACCURACY
The LTC2414/LTC2418 are designed to reduce as much as
possible the conversion result sensitivity to device
decoupling, PCB layout, antialiasing circuits, line fre-
24
(INTERNAL)
SDO
SCK
SDI
CS
CONVERSION
DON’T CARE
U
(1)
BIT 31
EOC
U
BIT 30
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
(0)
W
BIT 29
SIG
EN
BIT 28
MSB
SGL
U
0.1V TO V
REFERENCE
ANALOG
INPUTS
VOLTAGE
BIT 27
1µF
2.7V TO 5.5V
ODD/
SIGN
CC
•
•
•
•
•
•
11
12
21
28
10
9
1
8
BIT 26
V
REF
REF
CH0
CH7
CH8
CH15
COM
A2
CC
•
•
•
•
•
•
LTC2414/
LTC2418
+
–
quency perturbations and so on. Nevertheless, in order to
preserve the extreme accuracy capability of this part,
some simple precautions are desirable.
Digital Signal Levels
The LTC2414/LTC2418’s digital interface is easy to use.
Its digital inputs (SDI, F
of operation) accept standard TTL/CMOS logic levels and
the internal hysteresis receivers can tolerate edge rates as
slow as 100µs. However, some considerations are required
to take advantage of the exceptional accuracy and low
supply current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(V
current from the power supply. It should be noted that,
when any one of the digital input signals (SDI, F
SCK in External SCK mode of operation) is within this
range, the power supply current may increase even if the
signal in question is at a valid logic level. For micropower
DATA OUTPUT
CC
BIT 25
SDO
GND
SCK
SDI
CS
F
O
A1
– 0.5V), the CMOS input receiver draws additional
17
15
20
18
19
16
BIT 24
A0
3-WIRE
SPI INTERFACE
V
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
O
, CS and SCK in External SCK mode
BIT 6
DON’T CARE
LSB
PARITY
BIT 0
CONVERSION
O
, CS and
241418 F10
241418fa