LTC2414 LINER [Linear Technology], LTC2414 Datasheet - Page 25

• Manufacturer Part Number: LTC2414
• Description: 8-/16-Channel 24-Bit No Latency TM ADCs
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
operation, it is recommended to drive all digital input
signals to full CMOS levels [V
V
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the pins
may severely disturb the analog to digital conversion
process. Undershoot and overshoot can occur because of
the impedance mismatch at the converter pin when the
transition time of an external control signal is less than
twice the propagation delay from the driver to LTC2414/
LTC2418. For reference, on a regular FR-4 board, signal
propagation velocity is approximately 183ps/inch for
internal traces and 170ps/inch for surface traces. Thus, a
driver generating a control signal with a minimum transi-
tion time of 1ns must be connected to the converter pin
through a trace shorter than 2.5 inches. This problem
becomes particularly difficult when shared control lines
are used and multiple reflections may occur. The solution
is to carefully terminate all transmission lines close to
their characteristic impedance.
Parallel termination near the LTC2414/LTC2418 pin will
eliminate this problem but will increase the driver power
dissipation. A series resistor between 27Ω and 56Ω
placed near the driver or near the LTC2414/LTC2418 pin
will also eliminate this problem without additional power
dissipation. The actual resistor value depends upon the
trace impedance and connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The differential input and refer-
ence architecture reduce substantially the converter’s
sensitivity to ground currents.
Particular attention must be given to the connection of the
F
external conversion clock. This clock is active during the
conversion time and the normal mode rejection provided
by the internal digital filter is not very high at this fre-
quency. A normal mode signal of this frequency at the
converter reference terminals may result into DC gain and
INL errors. A normal mode signal of this frequency at the
converter input terminals may result into a DC offset error.
O
OH
signal when the LTC2414/LTC2418 are used with an
> (V
CC
– 0.4V)].
U
U
W
IL
< 0.4V and
U
Such perturbations may occur due to asymmetric capaci-
tive coupling between the F
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the F
nals. When the F
converter, substantial AC current is flowing in the loop
formed by the F
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the F
the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the LTC2414/LTC2418
converters are directly connected to a network of sampling
capacitors. Depending upon the relation between the
differential input voltage and the differential reference
voltage, these capacitors are switching between these
four pins transferring small amounts of charge in the
process. A simplified equivalent circuit is shown in
Figure 11.
For a simple approximation, the source impedance R
driving an analog input pin (IN
considered to form, together with R
Figure 11), a first order passive network with a time
constant τ = (R
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
When using the internal oscillator (F
LTC2414/LTC2418’s front-end switched-capacitor net-
work is clocked at 76800Hz corresponding to a 13µs
sampling period. Thus, for settling errors of less than
1ppm, the driving source impedance should be chosen
such that τ ≤ 13µs/14 = 920ns. When an external oscillator
of frequency f
and, for a settling error of less than 1ppm, τ ≤ 0.14/f
EOSC
O
O
S
signal trace and the input/reference sig-
connection trace, the termination and the
O
+ R
is used, the sampling period is 2/f
signal is parallel terminated near the
LTC2414/LTC2418
SW
O
signal as well as the loop area for
) • C
O
signal trace and the converter
EQ
+
, IN
. The converter is able to
–
, REF
O
= LOW or HIGH), the
SW
+
or REF
and C
–
) can be
EQ
25
241418fa
EOSC
EOSC
(see
S
.