RJ80535 Intel, RJ80535 Datasheet - Page 21

• Manufacturer Part Number: RJ80535
• Description: Pentium M Processor
• Manufacturer: Intel

3.8
Intel
®
Table 3.
Pentium
®
System Bus Pin Groups
NOTES:
1. BPM[2:0]# and PRDY# are AGTL+ output only signals.
2. In processor systems where there is no debug port implemented on the system board, these signals are used
to support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects
CMOS Signals
CMOS input signals are shown in
signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. All of the CMOS
signals are required to be asserted for at least three BCLKs in order for the chipset to recognize
them. See
M Processor Datasheet
AGTL+ Common Clock Input
AGTL+ Common Clock I/O
AGTL+ Source Synchronous I/O
AGTL+ Strobes
CMOS Input
Open Drain Output
CMOS Output
CMOS Input
Open Drain Output
System Bus Clock
Power/Other
Signal Group
Section 3.10
for the DC specifications of the CMOS signal groups.
Synchronous
to BCLK[1:0]
Synchronous
to BCLK[1:0]
Synchronous
to associated
strobe
Synchronous
to BCLK[1:0]
Asynchronous
Asynchronous
Asynchronous
Synchronous
to TCK
Synchronous
to TCK
Clock
Table
Type
3. Legacy output FERR#, IERR# and other non-AGTL+
BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#,
TRDY#
ADS#, BNR#, BPM[3:0]#
HITM#, LOCK#, PRDY#
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
A20M#, DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/
NMI, PWRGOOD, SMI#, SLP#, STPCLK#
FERR#, IERR#, PROCHOT#, THERMTRIP#
PSI#, VID[5:0]
TCK, TDI, TMS, TRST#
BCLK[1:0], ITP_CLK[1:0]
COMP[3:0], DBR#
TEST1, THERMDA, THERMDC, V
V
TDO
CC
REQ[4:0]#, A[16:3]#
A[31:17]#
D[15:0]#, DINV0#
D[31:16]#, DINV1#
D[47:32]#, DINV2#
D[63:48]#, DINV3#
Q
[1:0], V
Signals
CC _SENSE
2
, GTLREF, RSVD, TEST3, TEST2,
, V
1
SS,
Signals
1
Electrical Specifications
, BR0#, DBSY#, DRDY#, HIT#,
V
ADSTB[0]#
ADSTB[1]#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
SS_SENSE
Associated Strobe
CC
, V
CCA
[3:0], V
CC
P,
21