ADC1213D080HN/C1 NXP [NXP Semiconductors], ADC1213D080HN/C1 Datasheet
ADC1213D080HN/C1
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ADC1213D080HN/C1 Summary of contents
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ADC1213D series Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 05 — 23 April 2010 1. General description The ADC1213D is a dual-channel 12-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Sampling frequency (Msps) ADC1213D125HN/C1 125 ADC1213D105HN/C1 105 ADC1213D080HN/C1 80 ADC1213D065HN/ Block diagram INAP T/H INPUT STAGE INAM CLKP DLL PLL CLKM INBP T/H INPUT STAGE INBM ADC1213D Fig 1. Block diagram ADC1213D_SER_5 Preliminary data sheet ...
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NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Symbol INAP INAM VCMA REFAT REFAB AGND CLKP CLKM AGND REFBB REFBT VCMB ADC1213D_SER_5 Preliminary data sheet 1 INAP INAM 2 VCMA 3 REFAT 4 5 ...
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NXP Semiconductors Table 2. Symbol INBM INBP VDDA VDDA SCLK/DCS SDIO/DCS CS AGND RESET SCRAMBLER CFG0 CFG1 CFG2 CFG3 VDDD DGND DGND DGND VDDD CMLPB CMLNB VDDD DGND DGND VDDD CMLNA CMLPA VDDD DGND DGND SYNCP SYNCN DGND VDDD SWING_0 ...
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NXP Semiconductors Table 2. Symbol AGND VDDA SENSE VREF VDDA [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. [2] OTRA stands for “OuT of Range” A. OTRB stands for “OuT of Range” Limiting values ...
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NXP Semiconductors [1] Table 5. Characteristics …continued Symbol Parameter I digital supply current DDD P total power dissipation tot P power dissipation Digital inputs Clock inputs: pins CLKP and CLKM, AC coupled LVPECL V differential clock input i(clk)dif voltage LVDS ...
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NXP Semiconductors [1] Table 5. Characteristics …continued Symbol Parameter Analog inputs: pins INAP, INAM, INBP, and INBM I input current I R input resistance I C input capacitance I V common-mode input I(cm) voltage B input bandwidth i V differential ...
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NXP Semiconductors [1] Table 5. Characteristics …continued Symbol Parameter Output levels 1.8 V; SWING_SEL[2:0] = 100 DDD V LOW-level output OL voltage V HIGH-level output OH voltage Serial configuration: SYNCCP, SYNCCN V LOW-level input voltage IL V High-level ...
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Dynamic characteristics [1] Table 6. Characteristics Symbol Parameter Conditions Analog signal processing α second harmonic level MHz MHz MHz 170 MHz i α third ...
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Table 6. Characteristics …continued Symbol Parameter Conditions IMD intermodulation distortion MHz MHz MHz 170 MHz i α crosstalk between MHz ct(ch) i ...
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Clock and digital output timing [1] Table 7. Characteristics Symbol Parameter Conditions Clock timing input: pins CLKP and CLKM f clock frequency clk t data latency time clock cycles lat(data) δ clock duty cycle DCS_EN = 1: clk en ...
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NXP Semiconductors 12. Serial output timings The eye diagram of the serial output is shown in are: • 3.125 Gbps data rate • T amb • DC coupling with two different receiver common-mode voltages Fig 3. Fig 4. ADC1213D_SER_5 Preliminary ...
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NXP Semiconductors 13. SPI timing Table 8. Characteristics Symbol Parameter Serial Peripheral Interface timings t SCLK pulse width w(SCLK) t SCLK HIGH pulse width w(SCLKH) t SCLK LOW pulse width w(SCLKL) t set-up time su t hold time h f ...
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NXP Semiconductors Fig 6. The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters ...
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NXP Semiconductors Table 9. Input frequency 3 MHz 70 MHz 170 MHz 14.1.3 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Fig 8. Fig 9. The configuration shown in both cases, ...
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NXP Semiconductors 14.2 System reference and power management 14.2.1 Internal/external reference The ADC1213D has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pin VREF ...
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NXP Semiconductors VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE Fig 11. Internal reference (p-p) full-scale VREF 0.1 μF V SENSE VDDA Fig 13. External reference (p- (p-p) full-scale 14.2.2 Reference gain control The ...
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NXP Semiconductors Fig 15. Reference equivalent schematic 14.2.4 Biasing The common-mode output voltage, V common-mode input voltage, V (pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal performance. 14.3 Clock input 14.3.1 Drive ...
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NXP Semiconductors a. Sine clock input c. LVDS clock input Fig 17. Differential clock input 14.3.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in voltage of the differential input stage is set via internal ...
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NXP Semiconductors If single-ended is implemented without setting SE_SEL accordingly, the unused pin should be connected to ground via a capacitor. 14.3.3 Clock input divider The ADC1413D contains an input clock divider that divides the incoming clock by a factor ...
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NXP Semiconductors Fig 20. CML output connection to the receiver in AC coupling 14.5 JESD204A serializer 14.5.1 Digital JESD204A formatter The block placed after the ADC cores is used to implement all functionalities of the JESD204A standard. This ensures signal ...
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NXP Semiconductors ADC_MODE[1:0] PRBS 11 N DUMMY & CS ADC_PD ADC A × 1 frame CLK PLL × F char CLK AND DLL × 10F bit CLK ADC B ...
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NXP Semiconductors Table 13. INP-INM (V) .... +0.9980469 +0.9985352 +0.9990234 +0.9995117 +1.0000000 > +1 14.6 Serial Peripheral Interface (SPI) 14.6.1 Register description The ADC1213D serial interface is a synchronous serial communications port allowing for easy interfacing with many industry microprocessors. ...
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NXP Semiconductors Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is incremented to access subsequent addresses. ...
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Table 17. Register allocation map [1] Addr Register name R/W Bit definition Hex Bit 7 Bit 6 ADC control register 0003 Channel index R/W 0005 Reset and R/W SW_ Operating modes RST 0006 Clock R/W - 0008 Vref R/W - ...
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Table 17. Register allocation map …continued [1] Addr Register name R/W Bit definition Hex Bit 7 Bit 6 0826 Cfg_7_CS_N R/W* 0 0827 Cfg_8_Np R 0 0828 Cfg_9_S R/W* 0 0829 Cfg_10_HD_CF R/W* HD 082C Cfg_01_2_LID R/W* 0 082D Cfg_02_2_LID ...
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NXP Semiconductors 14.6.3 Register description 14.6.3.1 ADC control register Table 18. Register channel Index (address 0003h) Bit Symbol Access RESERVED[5: ADCB R/W 0 ADCA R/W Table 19. Register reset and Power-down mode (address 0005h) Bit ...
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NXP Semiconductors Table 21. Register Vref (address 0008h) Bit Symbol Access INTREF_EN R INTREF[2:0] R/W Table 22. Digital offset adjustment (address 0013h) Register offset: (address 0013h) Decimal +31 ... 0 ... ...
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NXP Semiconductors Table 25. Register test pattern 3 (address 0016h) Bit Symbol Access TESTPAT_3[5:0] R 14.6.4 JESD204A digital control registers Table 26. SER status (address 0801h) Bit Symbol Access 7 RXSYNC_ERROR R/W ...
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NXP Semiconductors Table 28. SER cfg set-up (address 0803h) Bit Symbol Access CFG_SETUP[3:0] R/W [1] The default value for this register depends on the external pull-up/pull-down on CFG0, CFG1, CFG2 or CFG3. ...
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NXP Semiconductors Table 29. SER control1 (address 0805h) Bit Symbol 2 REV_SCR 1 REV_ENCODER 0 REV_SERIAL Table 30. SER control2 (address 0806h) Bit Symbol SWAP_LANE_1_2 0 SWAP_ADC_0_1 Table 31. SER analog ctrl (address 0808h) Bit ...
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NXP Semiconductors Table 34. SER PRBS Ctrl (address 080Bh) Bit Symbol PRBS_TYPE[1:0] Table 35. Cfg_0_DID (address 0820h) Bit Symbol DID[7:0] Table 36. Cfg_1_BID (address 0821h) Bit Symbol ...
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NXP Semiconductors Table 41. Cfg_7_CS_N (address 0826h) Bit Symbol CS[ N[3:0] Table 42. Cfg_8_Np (address 0827h) Bit Symbol NP[4:0] Table 43. Cfg_9_S (address ...
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NXP Semiconductors Table 48. Cfg01_13_fchk (address 084Dh) Bit Symbol FCHK[7:0] Table 49. LaneA_0_ctrl (address 0870h) Bit Symbol SCR_IN_MODE LANE_MODE[1: LANE_POL 1 LANE_CLK_POS_EDGE R/W 0 Lane_PD Table 50. LaneB_0_ctrl ...
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NXP Semiconductors Table 50. LaneB_0_ctrl (address 0871h) Bit Symbol LANE_MODE[1: LANE_POL 1 LANE_CLK_POS_EDGE R/W 0 Lane_PD Table 51. ADCA_0_ctrl (address 0890h) Bit Symbol ADC_MODE[1: ...
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NXP Semiconductors Table 52. ADCB_0_ctrl (address 0891h) Bit Symbol 0 ADC_PD ADC1213D_SER_5 Preliminary data sheet …continued Access Value Description R/W ADC power-down control: 0 ADC is operational 1 ADC is in Power-down mode All information provided in this document is ...
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NXP Semiconductors 15. Package outline HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 0.85 mm terminal 1 index area terminal 1 56 index ...
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NXP Semiconductors 16. Revision history Table 53. Revision history Document ID ADC1213D_SER_5 Modifications: ADC1213D_SER_4 ADC1213D065_080_105_125_3 20090617 ADC1213D065_080_105_125_2 20090604 ADC1213D065_080_105_125_1 20090528 ADC1213D_SER_5 Preliminary data sheet Release date Data sheet status 20100423 Preliminary data sheet • Product status changed from Objective to ...
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NXP Semiconductors 17. Legal information 17.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use neither qualified nor tested in accordance with automotive testing ...
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NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . ...