ADC1213D080HN/C1 NXP [NXP Semiconductors], ADC1213D080HN/C1 Datasheet - Page 33

• Manufacturer Part Number: ADC1213D080HN/C1
• Description: Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
ADC1213D_SER_5
Preliminary data sheet
Bit
7
6
5 to 4
3 to 0
Bit
7 to 5
4 to 0
Bit
7 to 1
0
Bit
7
6 to 2
1 to 0
Bit
7 to 5
4 to 0
Bit
7 to 5
4 to 0
Bit
7 to 0
Symbol
-
CS[0]
-
N[3:0]
Symbol
-
NP[4:0]
Symbol
-
S
Symbol
HD
-
CF[1:0]
Symbol
-
LID[4:0]
Symbol
-
LID[4:0]
Symbol
FCHK[7:0]
Cfg_7_CS_N (address 0826h)
Cfg_8_Np (address 0827h)
Cfg_9_S (address 0828h)
Cfg_10_HD_CF (address 0829h)
Cfg01_2_LID (address 082Ch)
Cfg02_2_LID (address 082Dh)
Cfg02_13_fchk (address 084Ch)
R
R
R/W
Access
R
R/W
R/W
Access
R
R/W
Access
R/W
Access
R/W
R
Access
R
R/W
Access
R
R/W
Access
R
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Value
0
*
00
****
Value
000
*****
Value
0000000
1
Value
*
00000
**
Value
000
11011
Value
000
11100
Value
********
Rev. 05 — 23 April 2010
Description
not used
defines the number of control bits per sample, minus 1
not used
defines the converter resolution
Description
not used
defines the total number of bits per sample, minus 1
Description
not used
defines number of samples per converter per frame cycle
Description
defines high density format
not used
defines number of control words per frame clock cycle per link.
Description
not used
defines lane1 identification number
Description
not used
defines lane2 identification number
Description
defines the checksum value for lane1
checksum corresponds to the sum of all the link configuration
parameters modulo 256 (as defined in JEDEC Standard
No.204A)
ADC1213D series
ADC1213D series
© NXP B.V. 2010. All rights reserved.
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