DAC1008D750HN NXP [NXP Semiconductors], DAC1008D750HN Datasheet - Page 13

• Manufacturer Part Number: DAC1008D750HN
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1008D750
Product data sheet
Fig 3.
SYNC_OUT
lane#
The descrambler can be enabled/disabled
JESD204A receiver
DES
10.2 JESD204A receiver
10b
The JEDEC204A defines the following parameters:
The DAC1008D750 supports both LMF = 421 and LMF = 211. The current setting is
configurable via the SPI registers interface.
The complete Digital Layer Processing (DLP) adds a variable delay on each lane path.
This is mainly because of the inter-lane alignment.
Table 6.
[1]
[2]
Symbol Parameter
t
d
CLOCK
ALIGN
frame
clock
D = guaranteed by design.
Frame clock cycle.
10b
delay time
Digital Layer Processing Latency
L is the number of lanes per link
M is the number of converters per device
F is the number of bytes per frame clock period
WORD
ALIGN
SYNC
All information provided in this document is subject to legal disclaimers.
AND
Conditions
digital layer processing
delay
Rev. 2 — 5 January 2011
10b
K-DETECT
10b/8b
RX CONTROLLER
8b
2×, 4× or 8× interpolating DAC with JESD204A
DESCRAMBLER
Test
D
[1]
8b
Min
13
DAC1008D750
Typ
-
8b
8b
8b
8b
© NXP B.V. 2011. All rights reserved.
Max
28
10b
10b
configuration
interface
internal
005aaa157
Unit
cycle
13 of 99
[2]