ADSP-21266_07 AD [Analog Devices], ADSP-21266_07 Datasheet - Page 18

• Manufacturer Part Number: ADSP-21266_07
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-21266
Power-Up Sequencing
The timing requirements for DSP startup are given in
and
Table 12. Power-Up Sequencing (DSP Startup)
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristic
t
Valid V
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to the crystal oscillator manufacturer’s data sheet for startup time.
Based on CLKIN cycles.
Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
The 4096 cycle count depends on t
RSTVDD
IVDDEVDD
CLKVDD
CLKRST
PLLRST
CORERST
depending on the design of the power supply subsystem.
Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
propagate default states at all I/O pins.
cycles maximum.
Figure
DDINT
/V
7.
DDEXT
assumes that the supplies are fully ramped to their 1.2 V and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
CLK_CFG1–0
RESET Low Before V
V
CLKIN Valid After V
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
DSP Core Reset Deasserted After RESET Deasserted
V DDEXT
RSTOUT
V DDINT
DDINT
RESET
CLKIN
SRST
On Before V
*
specification in
*
MULTIPLEXED WITH CLKOUT
t
RSTVDD
DDEXT
DDINT
DDINT
Table
/V
/V
DDEXT
14. If setup time is not met, one additional CLKIN cycle can be added to the core reset time, resulting in 4097
DDEXT
Rev. C | Page 18 of 44 | October 2007
Valid
Figure 7. Power-Up Sequencing
On
Table 12
1
t
IVDDEVDD
t
PLLRST
t
t
CLKVDD
CLKRST
Min
0
–50
0
10
20
4096 × t
t
2
3
CORERST
CK
4, 5
Max
200
200
Unit
ns
ms
ms
μs
μs