ADSP-21266_07 AD [Analog Devices], ADSP-21266_07 Datasheet - Page 5

• Manufacturer Part Number: ADSP-21266_07
• Description: Embedded Processor
• Manufacturer: AD [Analog Devices]

Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each
processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2126x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0–R15 and in PEY as S0–S15.
(OPTI ONAL)
(OP TIONAL)
DAC
CLOCK
ADC
S DAT
S DAT
CLK
CLK
FS
FS
2
2
3
CLKI N
XTAL
CLK_ CFG 1– 0
BOOTCFG1– 0
FLAG 3– 1
DAI_ P19
DAI_ P1 8
DAI_P 20
DAI_ P1
DAI_P 2
DAI_P 3
DAI
RESE T
ADS P-21266
SRU
CLK
FS
Figure 2. ADSP-21266 System Sample Configuration
PCG A
P CGB
SCLK0
SFS0
SD0A
SD0B
Rev. C | Page 5 of 44 | October 2007
S PORT0
SP ORT1
SPO RT2
S PORT3
SPO RT4
SPORT5
J TAG
6
CLKOUT
AD15 –0
FLAG0
ALE
W R
RD
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21266 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see
gram and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a
single cycle.
Instruction Cache
The ADSP-21266 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21266’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and
Figure 1 on Page
LATCH
1). With the ADSP-21266’s separate pro-
ADDR
W E
DATA
OE
CS
BOOT ROM
PARALLE L
I/O DEVICE
RAM, ROM
PO RT
ADSP-21266