EPF10K100 ALTERA [Altera Corporation], EPF10K100 Datasheet - Page 56
EPF10K100
Manufacturer Part Number
EPF10K100
Description
Embedded Programmable Logic Device Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.EPF10K100.pdf
(128 pages)
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Figure 24. FLEX 10K Device Timing Model
56
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Clock/Input
Dedicated
Timing simulation and delay prediction are available with the
MAX+PLUS II Simulator and Timing Analyzer, or with industry-
standard EDA tools. The Simulator offers both pre-synthesis functional
simulation to evaluate logic design accuracy and post-synthesis timing
simulation with 0.1-ns resolution. The Timing Analyzer provides point-
to-point timing delay information, setup and hold time analysis, and
device-wide performance analysis.
Figure 24
to and from the various elements of the FLEX 10K device.
shows the overall timing model, which maps the possible paths
Element
Logic
Interconnect
Embedded Array
Block
Altera Corporation
I/O Element