XC2S100-5CS144I XILINX [Xilinx, Inc], XC2S100-5CS144I Datasheet
XC2S100-5CS144I
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XC2S100-5CS144I Summary of contents
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R DS001 June 13, 2008 This document includes all four modules of the Spartan Module 1: Introduction and Ordering Information DS001-1 (v2.8) June 13, 2008 • Introduction • Features • General Overview • Product Availability • User I/O Chart • ...
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... Device Cells (Logic and RAM) XC2S15 432 15,000 XC2S30 972 30,000 XC2S50 1,728 50,000 XC2S100 2,700 100,000 XC2S150 3,888 150,000 XC2S200 5,292 200,000 Notes: 1. All user I/O counts do not include the four global clock/user input pins. See details in © 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners ...
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R General Overview The Spartan-II family of FPGAs have a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks (IOBs). There are four Delay-Locked Loops (DLLs), one at each corner of the ...
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... These pins are not included in user I/O counts. Table 2: Spartan-II FPGA User I/O Chart Maximum VQ100 Device User I/O VQG100 XC2S15 86 XC2S30 92 XC2S50 176 XC2S100 176 XC2S150 260 XC2S200 284 Notes: 1. All user I/O counts do not include the four global clock/user input pins. 2. Discontinued by PDN2004-01. DS001-1 (v2.8) June 13, 2008 Product Specification ...
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... Speed Grade Package Type Device Ordering Options Device Speed Grade XC2S15 -5 Standard Performance XC2S30 -6 Higher Performance XC2S50 XC2S100 XC2S150 XC2S200 Notes: 1. The -6 speed grade is exclusively available in the Commercial temperature range. Device Part Marking Device Type Operating Range DS001-1 (v2.8) June 13, 2008 Product Specification ...
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R Revision History Date Version No. 09/18/00 2.0 Sectioned the Spartan-II Family data sheet into four modules. Added industrial temperature range information. 10/31/00 2.1 Removed Power down feature. 03/05/01 2.2 Added statement on PROMs. 11/01/01 2.3 Updated Product Availability chart. ...
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R DS001-2 (v2.8) June 13, 2008 Architectural Description Spartan-II FPGA Array ® The Spartan -II field-programmable gate array, shown in Figure 2, is composed of five major configurable elements: • IOBs provide the interface between the package pins and the ...
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R The three IOB registers function either as edge-triggered D-type flip-flops or as level-sensitive latches. Each IOB has a clock signal (CLK) shared by the three registers and independent Clock Enable (CE) signals for each register. In addition to the ...
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R drivers are disabled. Maintaining a valid logic level in this way helps eliminate bus chatter. Because the weak-keeper circuit uses the IOB input buffer to monitor the input level, an appropriate V be provided if the signaling standard requires ...
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R Figure 4: Spartan-II CLB Slice (two identical slices in each CLB) Storage Elements Storage elements in the Spartan-II FPGA slice can be configured either as edge-triggered D-type flip-flops or as level-sensitive latches. The D inputs can be driven either ...
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... Table 5: Spartan-II Block RAM Amounts Spartan-II Device # of Blocks XC2S15 4 XC2S30 6 XC2S50 8 XC2S100 10 XC2S150 12 XC2S200 14 DS001-2 (v2.8) June 13, 2008 Product Specification Spartan-II FPGA Family: Functional Description Each block RAM cell, as illustrated in synchronous dual-ported 4096-bit RAM with independent control signals for each port. The data widths of the two ports can be configured independently, providing built-in bus-width conversion ...
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R Local Routing The local routing resources, as shown in the following three types of connections: • Interconnections among the LUTs, flip-flops, and General Routing Matrix (GRM) • Internal CLB feedback paths that provide high-speed connections to LUTs within the ...
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R CLB Figure 7: BUFT Connections to Dedicated Horizontal Bus Lines Clock Distribution The Spartan-II family provides high-speed, low-skew clock distribution through the primary global routing resources described above. A typical clock distribution net is shown in Figure 8. Four ...
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R Boundary-scan operation is independent of individual IOB configurations, and unaffected by package type. All IOBs, including unbonded ones, are treated as independent 3-state bidirectional pins in a single scan chain. Retention of the bidirectional test capability after configuration facilitates ...
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R Figure diagram of the Spartan-II family boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. IOB IOB IOB IOB IOB ...
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R TDO.T Bit 0 ( TDO end) TDO.O Bit 1 Bit 2 Top-edge IOBs (Right to Left) Left-edge IOBs (Top to Bottom) MODE.I Bottom-edge IOBs (Left to Right) Right-edge IOBs (Bottom to Top) (TDI end) BSCANT.UPD Figure 10: Boundary Scan ...
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... They will stay in effect until GTS is released during startup, after which the UnusedPin bitstream generator option will determine whether the unused I/Os have a pull-up, pull-down resistor. DS001-2 (v2.8) June 13, 2008 Product Specification Table 8: Spartan-II Configuration File Size Device XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 Modes Spartan-II devices support the following four configuration modes: • Slave Serial mode • ...
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R Signals There are two kinds of pins that are used to configure Spartan-II devices: Dedicated pins perform only specific configuration-related functions; the other pins can serve as general purpose I/Os once user operation has begun. The dedicated pins comprise ...
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R ( PROGRAM INIT . Symbol T Power-on reset POR T Program latency PL T CCLK output delay (Master Serial mode only) ICCK T Program pulse width PROGRAM Notes: (referring to waveform above:) 1. Before configuration can begin, ...
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R By default, these operations are synchronized to CCLK. The entire start-up sequence lasts eight cycles, called C0-C7, after which the loaded design is fully functional. The default timing for start-up is shown in the top half of Figure 13. ...
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R Slave Serial Mode In Slave Serial mode, the FPGA’s CCLK pin is driven by an external source, allowing FPGAs to be configured from other logic devices such as microprocessors daisy-chain configuration. Figure 15 a Master Serial ...
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R DIN CCLK DOUT (Output) . Symbol T DCC T CCD T CCO T CCH T CCL F CC DS001-2 (v2.8) June 13, 2008 Product Specification T T CCD DCC T CCH T CCO Description DIN setup DIN hold DOUT ...
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R Master Serial Mode In Master Serial mode, the CCLK output of the FPGA drives a Xilinx PROM which feeds a serial stream of configuration data to the FPGA’s DIN input. Figure 15 Serial FPGA configuring a Slave Serial FPGA ...
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R DATA[7:0] CCLK WRITE BUSY CS(0) 330Ω DONE INIT PROGRAM Figure 18: Slave Parallel Configuration Circuit Diagram Multiple Spartan-II FPGAs can be configured using the Slave Parallel mode, and be made to start-up simultaneously. To configure multiple devices in this ...
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R If CCLK is slower than F , the FPGA will never assert CCNH BUSY. In this case, the above handshake is unnecessary, and data can simply be entered into the FPGA every CCLK cycle. After INIT Goes High User ...
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R CCLK CS WRITE T SMCCW T SMDCC DATA[7:0] T SMCKBY BUSY No Write Symbol T SMDCC T SMCCD T SMCSCC T SMCCCS T CCLK SMCCW T SMWCC T SMCKBY CCNH CCLK CS WRITE DATA[7:0] BUSY DS001-2 ...
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R Design Considerations This section contains more detailed design information on the following features: • Delay-Locked Loop . . . see page 27 • Block RAM . . . see page 32 • Versatile I see page ...
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R BUFGDLL Pin Descriptions Use the BUFGDLL macro as the simplest way to provide zero propagation delay for a high-fanout on-chip clock from an external input. This macro uses the IBUFG, CLKDLL and BUFG primitives to implement the most basic ...
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R division factor N except for non-integer division in High Frequency (HF) mode. For division factor 1.5 the duty cycle in the HF mode is 33.3% High and 66.7% Low. For division factor 2.5, the duty cycle in the HF ...
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R Startup Delay Property This property, STARTUP_WAIT, takes on a value of TRUE or FALSE (the default value). When TRUE the Startup Sequence following device configuration is paused at a user-specified point until the DLL locks. Configuration and Readback of ...
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R Useful Application Examples The Spartan-II FPGA DLL can be used in a variety of creative and useful applications. The following examples show some of the more common applications. Standard Usage The circuit shown in Figure 28 resembles the BUFGDLL ...
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R Using Block RAM Features The Spartan-II FPGA family provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block RAM memory can be independently configured as a read/write port, a read ...
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R Table 11: Available Library Primitives Primitive Port A Width RAMB4_S4 4 RAMB4_S4_S4 RAMB4_S4_S8 RAMB4_S4_S16 RAMB4_S8 8 RAMB4_S8_S8 RAMB4_S8_S16 RAMB4_S16 16 RAMB4_S16_S16 Port Signals Each block RAM port operates independently of the others while accessing the same set of 4096 ...
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R Creating Larger RAM Structures The block RAM columns have specialized routing to allow cascading blocks together with minimal routing delays. This achieves wider or deeper RAM structures with a smaller timing penalty than when using normal routing channels. Location ...
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R CLK ADDR DIN DOUT EN RST WE DISABLED Figure 33: Timing Diagram for Single-Port Block RAM Memory CLK_A ADDR_A 00 EN_A T BCCS WE_A DI_A AAAA DO_A CLK_B ADDR_B 00 EN_B WE_B DI_B 1111 1111 DO_B MEM (00) Figure ...
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R At the third rising edge of CLKA, the T violated with two writes to memory location 0x0F. The DOA and DOB busses reflect the contents of the DIA and DIB busses, but the stored value at 0x7E is invalid. ...
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R support of a wide variety of applications, from general purpose standard applications to high-speed low-voltage memory busses. Versatile I/O blocks also provide selectable output drive strengths and programmable slew rates for the LVTTL output buffers, as well as an ...
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R PCI — Peripheral Component Interface The Peripheral Component Interface (PCI) standard specifies support for both 33 MHz and 66 MHz PCI bus applications. It uses a LVTTL input buffer and a push-pull output buffer. This standard does not require ...
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R the LOC property is described below. the input standards compatibility requirements. An optional delay element is associated with each IBUF. When the IBUF drives a flip-flop within the IOB, the delay element by default activates to ensure a zero ...
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R LVTTL output buffers have selectable drive strengths. The format for LVTTL OBUF primitive names is as follows. OBUF_<slew_rate>_<drive_strength> <slew_rate> is either F (Fast (Slow) and <drive_strength> is specified in milliamps ( 12, 16, or ...
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R IOBUF_<slew_rate>_<drive_strength> <slew_rate> can be either F (Fast (Slow) and <drive_strength> is specified in milliamps ( 12, 16, or 24). IOBUF DS001_40_061200 Figure 40: Input/Output Buffer Primitiveprimitive (IOBUF) When the IOBUF ...
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R property. This property could have one of the following seven values. DRIVE=2 DRIVE=4 DRIVE=6 DRIVE=8 DRIVE=12 (Default) DRIVE=16 DRIVE=24 Design Considerations Reference Voltage (V ) Pins REF Low-voltage I/O standards with a differential amplifier input buffer require an input ...
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R ground metallization. The IC internal ground level deviates from the external system ground level for a short duration (a few nanoseconds) after multiple outputs change state simultaneously. Ground bounce affects stable Low outputs and all inputs because they interpret ...
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R GTL A sample circuit illustrating a valid termination technique for GTL is shown in Figure 42. Table 20 specifications for the GTL standard. See Specifications" in Module 3 for the actual FPGA characteristics. GTL V = 1.2V TT 50Ω ...
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R HSTL Class III A sample circuit illustrating a valid termination technique for HSTL_III appears in Figure 45. DC voltage specifications appear in Table 23 for the HSTL_III standard. See Specifications" in Module 3 for the actual FPGA characteristics. HSTL ...
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R SSTL3 Class I A sample circuit illustrating a valid termination technique for SSTL3_I appears in Figure 47. DC voltage specifications appear in Table 25 for the SSTL3_I standard. See Specifications" in Module 3 for the actual FPGA characteristics. SSTL3 ...
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R SSTL2_I A sample circuit illustrating a valid termination technique for SSTL2_I appears in Figure 49. DC voltage specifications appear in Table 27 for the SSTL2_I standard. See Specifications" in Module 3 for the actual FPGA characteristics SSTL2 Class I ...
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R CTT A sample circuit illustrating a valid termination technique for CTT appear in Figure 51. DC voltage specifications appear in Table 29 for the CTT standard. See Module 3 for the actual FPGA characteristics . CTT V = 3.3V ...
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R LVTTL LVTTL requires no termination. DC voltage specifications appears in Table 32 for the LVTTL standard. See Specifications" in Module 3 for the actual FPGA characteristics. Table 32: LVTTL Voltage Specifications Parameter Min V 3.0 CCO V - REF ...
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R Revision History Date Version 09/18/00 2.0 Sectioned the Spartan-II Family data sheet into four modules. Corrected banking description. 03/05/01 2.1 Clarified guidelines for applying power to V 09/03/03 2.2 The following changes were made: • "Serial Modes," page 20 ...
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R DS001-3 (v2.8) June 13, 2008 Definition of Terms In this document, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, ...
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... Measurement Methodology," page 60 CCO Description voltage (below which configuration data voltage (below which configuration data may (1) XC2S15 Commercial Industrial XC2S30 Commercial Industrial XC2S50 Commercial Industrial XC2S100 Commercial Industrial XC2S150 Commercial Industrial XC2S200 Commercial Industrial (1) pin (2) VQ, CS, TQ, PQ, FG packages = 0V ...
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R Power-On Requirements Spartan-II FPGAs require that a minimum supply current I be provided to the V lines for a successful CCPO CCINT power-on. If more current is available, the FPGA can consume more than I minimum, though this cannot ...
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... All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan-II devices unless otherwise noted. Device All "Constants for Calculating TIOOP" 61. Device XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 "Constants for Calculating TIOOP" 61. www.xilinx.com ...
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... For a global clock input with standards other than LVTTL, adjust delays with values from the Global Clock Input Adjustments," page DS001-3 (v2.8) June 13, 2008 Product Specification Spartan-II FPGA Family: DC and Switching Characteristics Device All (1) 61. Device XC2S15 XC2S30 (1) XC2S50 XC2S100 XC2S150 XC2S200 61. www.xilinx.com Speed Grade -6 -5 Min Min Units 1 1 " ...
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... DS001-3 (v2.8) June 13, 2008 Product Specification Spartan-II FPGA Family: DC and Switching Characteristics (1) 57. Description Device All All All XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 All (2) All (1) XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 All All All All www.xilinx.com Speed Grade -6 -5 Min Max Min Max - 0.8 - 1.0 - 1 ...
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R IOB Input Delay Adjustments for Different Standards Input delays associated with the pad are specified for LVTTL. For other standards, adjust the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit. Symbol Description ...
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R IOB Output Switching Characteristics Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in Symbol Propagation Delays T O input ...
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R IOB Output Delay Adjustments for Different Standards Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values shown. A delay adjusted in ...
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R Calculation Function of IOOP Capacitance T is the propagation delay from the O Input of the IOB IOOP to the pad. The values for T are based on the standard IOOP capacitive load (C ) ...
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R Clock Distribution Guidelines Symbol GCLK Clock Skew T Global clock skew between IOB flip-flops GSKEWIOB Notes: 1. These clock distribution delays are provided for guidance only. They reflect the delays encountered in a typical design under worst-case conditions. Precise ...
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R DLL Timing Parameters All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark Symbol Description F Input clock frequency (CLKDLLHF) CLKINHF F Input clock frequency ...
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R Period Tolerance: the allowed input clock period change in nanoseconds CLKIN F CLKIN Output Jitter: the difference between an ideal reference clock edge and the actual design. Ideal Period Actual Period DS001-3 (v2.8) June 13, 2008 Product ...
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R CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise values are provided by the timing analyzer. Symbol Combinatorial Delays T 4-input function: F/G inputs to X/Y ...
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R CLB Arithmetic Switching Characteristics Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Symbol Combinatorial Delays T F operand inputs to ...
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R CLB Distributed RAM Switching Characteristics Symbol Sequential Delays T Clock CLK to X/Y outputs (WE active mode) SHCKO16 T Clock CLK to X/Y outputs (WE active mode) SHCKO32 Setup/Hold Times with Respect to ...
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R Block RAM Switching Characteristics Symbol Sequential Delays T Clock CLK to DOUT output BCKO Setup/Hold Times with Respect to Clock CLK ADDR inputs BACK BCKA DIN inputs BDCK BCKD ...
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... Removed Power Down feature. 01/19/01 2.2 DC and timing numbers updated to Preliminary for the XC2S50 and XC2S100. Industrial power-on current specifications and -6 DLL timing numbers added. Power-on specification clarified. 03/09/01 2.3 Added note on power sequencing. Clarified power-on current requirement. ...
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R DS001-4 (v2.8) June 13, 2008 Introduction This section describes how the various pins on a ® Spartan -II FPGA connect within the supported component packages, and provides device-specific thermal characteristics. Spartan-II FPGAs are available in both standard and Pb-free, ...
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R Table 36: Spartan-II Family Package Options Package Leads VQ100 / VQG100 100 Very Thin Quad Flat Pack (VQFP) TQ144 / TQG144 144 Thin Quad Flat Pack (TQFP) CS144 / CSG144 144 Chip Scale Ball Grid Array (CSBGA) PQ208 / ...
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... XC2S50 XC2S100 CS144 XC2S30 CSG144 XC2S50 XC2S100 PQ208 PQG208 XC2S150 XC2S200 XC2S50 XC2S100 FG256 FGG256 XC2S150 XC2S200 XC2S150 FG456 FGG456 XC2S200 DS001-4 (v2.8) June 13, 2008 Product Specification value similarly reports the difference between the board and junction temperature. The junction-to-ambient (θ ...
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R Pinout Tables The following device-specific pinout tables include all packages available for each Spartan the pad locations around the die, and include Boundary Scan register locations. XC2S15 Device Pinouts XC2S15 Pad Name Function Bank VQ100 TQ144 GND - P1 ...
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R XC2S15 Device Pinouts (Continued) XC2S15 Pad Name Function Bank VQ100 TQ144 GND - - P61 I/O (D5) 3 P57 P60 I/O 3 P58 P59 I/ P59 P58 REF I/O (D4) 3 P60 P57 I P56 ...
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R XC2S30 Device Pinouts XC2S30 Pad Name Function Bank VQ100 TQ144 CS144 PQ208 GND - P1 P143 TMS - P2 P142 I P141 I P140 I I/ P139 REF I/O ...
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R XC2S30 Device Pinouts (Continued) XC2S30 Pad Name Function Bank VQ100 TQ144 CS144 PQ208 P84 I P83 V - P42 P82 CCINT CCO ...
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R XC2S30 Device Pinouts (Continued) XC2S30 Pad Name Function Bank VQ100 TQ144 CS144 PQ208 V - P85 P24 CCINT I P23 I P22 GND ...
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R XC2S50 Device Pinouts XC2S50 Pad Name Function Bank TQ144 PQ208 GND - P143 TMS - P142 I/O 7 P141 I I/O 7 P140 I I GND - - I/ P139 REF ...
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R XC2S50 Device Pinouts (Continued) XC2S50 Pad Name Function Bank TQ144 PQ208 I/O 5 P99 P63 GND - P98 P64 P65 CCO V - P97 P66 CCINT I/O 5 P96 P67 I/O 5 P95 P68 I/O 5 ...
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R XC2S50 Device Pinouts (Continued) XC2S50 Pad Name Function Bank TQ144 PQ208 I I/O 3 P56 P127 V - P55 P128 CCINT (1) I/O, TRDY 3 P54 P129 V 3 P53 P130 CCO V 2 P53 P130 CCO ...
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R XC2S50 Device Pinouts (Continued) XC2S50 Pad Name Function Bank TQ144 PQ208 I I P188 I/ P12 P189 REF GND - - P190 I P191 I P192 I ...
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... TQ144 PQ208 FG256 GND - P143 P1 TMS - P142 P2 I/O 7 P141 P3 I I/O 7 P140 GND - - - CCO I/ P139 P6 REF DS001-4 (v2.8) June 13, 2008 Product Specification XC2S100 Device Pinouts (Continued) XC2S100 Pad Name - - Function I/O I/O E5 E12 I/O P3 P14 I/O I/O, V REF - - I GND V CCO - - V CCINT - - I I/O I I GND I/O, V REF F6 F7 ...
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... CCO I/ P102 P59 REF I P60 I I/O 5 P101 P61 I DS001-4 (v2.8) June 13, 2008 Product Specification XC2S100 Device Pinouts (Continued) XC2S100 Pad Name Bndry FG456 Scan Function I/O, V CCINT CCINT REF I/O CCO CCO Bank 6* Bank 6* GND GND* GND CCO K4 T1 ...
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... I/O 3 P64 P113 I I/ P63 P114 REF I/O (D6) 3 P62 P115 GND - P61 P116 DS001-4 (v2.8) June 13, 2008 Product Specification XC2S100 Device Pinouts (Continued) XC2S100 Pad Name Bndry FG456 Scan Function T11 AB16 502 V CCO - AB17 505 V CCINT N11 V15 508 I/O (D5) R12 Y16 511 ...
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... I P166 I I/ P27 P167 REF I/O 1 P26 P168 GND - P25 P169 DS001-4 (v2.8) June 13, 2008 Product Specification XC2S100 Device Pinouts (Continued) XC2S100 Pad Name Bndry FG456 Scan Function F12 G20 695 V CCO E15 F19 701 V CCINT F13 F21 704 I CCO CCO ...
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... R XC2S100 Device Pinouts (Continued) XC2S100 Pad Name Function Bank TQ144 PQ208 FG256 I P188 I/ P12 P189 REF GND - - P190 I P191 I P192 I P193 I I/O 0 P11 P194 I/O 0 P10 P195 P196 CCINT P197 CCO GND - P8 P198 I P199 I/ P200 REF I ...
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... Pins CCINT E5 E18 F6 F17 G9 G14 G15 G16 J7 J16 P7 P16 T14 U6 U17 V5 V18 V Bank 0 Pins CCO DS001-4 (v2.8) June 13, 2008 Product Specification Additional XC2S100 Package Pins (Continued) F10 F7 F13 F14 - - G17 H17 M16 N16 - - T12 T13 T10 T11 E5 E12 P3 P14 ...
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R XC2S150 Device Pinouts XC2S150 Pad Name Function Bank PQ208 FG256 GND - P1 GND* TMS - GND - - GND ...
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R XC2S150 Device Pinouts (Continued) XC2S150 Pad Name Function Bank PQ208 FG256 I/O 6 P46 I/O 6 P47 GND - - GND ...
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R XC2S150 Device Pinouts (Continued) XC2S150 Pad Name Function Bank PQ208 FG256 I/O 4 P90 V - P91 V CCINT V 4 P92 V CCO Bank 4* GND - P93 GND* I/O 4 P94 I/ P95 REF I/O ...
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R XC2S150 Device Pinouts (Continued) XC2S150 Pad Name Function Bank PQ208 FG256 (1) I/O, IRDY 2 P132 I/O 2 P133 I I/O 2 P134 I I/O (D3) 2 P135 I/ P136 REF V 2 ...
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R XC2S150 Device Pinouts (Continued) XC2S150 Pad Name Function Bank PQ208 FG256 I/O 1 P174 I I/O 1 P175 I/O 1 P176 GND - P177 GND CCO Bank 1* I/ P178 REF ...
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R Additional XC2S150 Package Pins PQ208 Not Connected Pins P55 P56 - - 11/02/00 FG256 V Pins CCINT C3 C14 D4 D13 M5 M12 N4 N13 V Bank 0 Pins CCO Bank 1 Pins CCO ...
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R XC2S200 Device Pinouts XC2S200 Pad Name Function Bank PQ208 FG256 GND - P1 GND* TMS - GND - - GND* I/ REF I/O ...
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R XC2S200 Device Pinouts (Continued) XC2S200 Pad Name Function Bank PQ208 FG256 I I/O 6 P43 GND - - GND I/O 6 P44 I/ P45 REF V ...
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R XC2S200 Device Pinouts (Continued) XC2S200 Pad Name Function Bank PQ208 FG256 I, GCK0 4 P80 I/O 4 P81 I I/O 4 P82 I I I/O 4 P83 I/ P84 REF V ...
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R XC2S200 Device Pinouts (Continued) XC2S200 Pad Name Function Bank PQ208 FG256 V 3 P117 V CCO Bank P118 V CCINT I/O (D5) 3 P119 I/O 3 P120 ...
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R XC2S200 Device Pinouts (Continued) XC2S200 Pad Name Function Bank PQ208 FG256 V 1 P156 V CCO Bank 1* TDO 2 P157 GND - P158 GND* TDI - P159 I/O (CS) 1 P160 I/O (WRITE) 1 P161 I ...
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R XC2S200 Device Pinouts (Continued) XC2S200 Pad Name Function Bank PQ208 FG256 GND - P198 GND* I/O 0 P199 I/ P200 REF I I/O 0 P201 GND - - GND ...
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R Additional XC2S200 Package Pins (Continued) 11/02/00 FG456 V Pins CCINT E5 E18 F6 F17 G9 G14 G15 G16 J7 J16 P7 P16 T14 U6 U17 V5 V18 V Bank 0 Pins CCO F10 ...