XC2S100-5CS144I XILINX [Xilinx, Inc], XC2S100-5CS144I Datasheet - Page 38

• Manufacturer Part Number: XC2S100-5CS144I
• Description: Spartan-II FPGA Family
• Manufacturer: XILINX [Xilinx, Inc]

PCI — Peripheral Component Interface
The Peripheral Component Interface (PCI) standard
specifies support for both 33 MHz and 66 MHz PCI bus
applications. It uses a LVTTL input buffer and a push-pull
output buffer. This standard does not require the use of a
reference voltage (V
(V
(V
are also 5V-tolerant.
GTL — Gunning Transceiver Logic Terminated
The Gunning Transceiver Logic (GTL) standard is a
high-speed bus standard (JESD8.3). Xilinx has
implemented the terminated variation of this standard. This
standard requires a differential amplifier input buffer and an
open-drain output buffer.
GTL+ — Gunning Transceiver Logic Plus
The Gunning Transceiver Logic Plus (GTL+) standard is a
high-speed bus standard (JESD8.3).
HSTL — High-Speed Transceiver Logic
The High-Speed Transceiver Logic (HSTL) standard is a
general purpose high-speed, 1.5V bus standard (EIA/JESD
8-6). This standard has four variations or classes. Versatile
I/O devices support Class I, III, and IV. This standard
requires a Differential Amplifier input buffer and a Push-Pull
output buffer.
SSTL3 — Stub Series Terminated Logic for 3.3V
The Stub Series Terminated Logic for 3.3V (SSTL3)
standard is a general purpose 3.3V memory bus standard
(JESD8-8). This standard has two classes, I and II.
Versatile I/O devices support both classes for the SSTL3
standard. This standard requires a Differential Amplifier
input buffer and an Push-Pull output buffer.
SSTL2 — Stub Series Terminated Logic for 2.5V
The Stub Series Terminated Logic for 2.5V (SSTL2)
standard is a general purpose 2.5V memory bus standard
(JESD8-9). This standard has two classes, I and II.
Versatile I/O devices support both classes for the SSTL2
standard. This standard requires a Differential Amplifier
input buffer and an Push-Pull output buffer.
CTT — Center Tap Terminated
The Center Tap Terminated (CTT) standard is a 3.3V
memory bus standard (JESD8-4). This standard requires a
Differential Amplifier input buffer and a Push-Pull output
buffer.
DS001-2 (v2.8) June 13, 2008
Product Specification
TT
CCO
), however, it does require a 3.3V output source voltage
). I/Os configured for the PCI, 33 MHz, 5V standard
R
REF
) or a board termination voltage
www.xilinx.com
AGP-2X — Advanced Graphics Port
The AGP standard is a 3.3V Advanced Graphics Port-2X
bus standard used with processors for graphics
applications. This standard requires a Push-Pull output
buffer and a Differential Amplifier input buffer.
Library Primitives
The Xilinx library includes an extensive list of primitives
designed to provide support for the variety of Versatile I/O
features. Most of these primitives represent variations of the
five generic Versatile I/O primitives:
•
•
•
•
•
These primitives are available with various extensions to
define the desired I/O standard. However, it is
recommended that customers use a a property or attribute
on the generic primitive to specify the I/O standard. See
"Versatile I/O
IBUF
Signals used as inputs to the Spartan-II device must source
an input buffer (IBUF) via an external input port. The generic
IBUF primitive appears in
is LVTTL when the generic IBUF has no specified extension
or property.
When the IBUF primitive supports an I/O standard such as
LVTTL, LVCMOS, or PCI33_5, the IBUF automatically
configures as a 5V tolerant input buffer unless the V
the bank is less than 2V. If the single-ended IBUF is placed
in a bank with an HSTL standard (V
buffer is not 5V tolerant.
The voltage reference signal is "banked" within the
Spartan-II device on a half-edge basis such that for all
packages there are eight independent V
internally. See
banks. Within each bank approximately one of every six I/O
pins is automatically configured as a V
IBUF placement restrictions require that any differential
amplifier input signals within a bank be of the same
standard. How to specify a specific location for the IBUF via
IBUF (input buffer)
IBUFG (global clock input buffer)
OBUF (output buffer)
OBUFT (3-state output buffer)
IOBUF (input/output buffer)
Spartan-II FPGA Family: Functional Description
Figure 35: Input Buffer (IBUF) Primitive
Properties".
Figure 36
I
for a representation of the I/O
Figure
IBUF
DS001_35_061200
35. The assumed standard
CCO
O
REF
REF
< 2V), the input
input.
banks
Module 2 of 4
CCO
for
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