XC2S100-5CS144I XILINX [Xilinx, Inc], XC2S100-5CS144I Datasheet - Page 31

• Manufacturer Part Number: XC2S100-5CS144I
• Description: Spartan-II FPGA Family
• Manufacturer: XILINX [Xilinx, Inc]

Useful Application Examples
The Spartan-II FPGA DLL can be used in a variety of
creative and useful applications. The following examples
show some of the more common applications.
Standard Usage
The circuit shown in
macro implemented to provide access to the RST and
LOCKED pins of the CLKDLL.
Deskew of Clock and Its 2x Multiple
The circuit shown in
multiplier and also uses the CLK0 clock output with zero ns
skew between registers on the same chip. A clock divider
circuit could alternatively be implemented using similar
connections.
Because any single DLL can only access at most two
BUFGs, any additional output clock signals must be routed
from the DLL in this example on the high speed backbone
routing.
Generating a 4x Clock
By connecting two DLL circuits each implementing a 2x
clock multiplier in series as shown in
multiply can be implemented with zero skew between
registers in the same device.
DS001-2 (v2.8) June 13, 2008
Product Specification
Figure 29: DLL Deskew of Clock and 2x Multiple
Figure 28: Standard DLL Implementation
IBUFG
IBUF
IBUFG
IBUF
R
CLKIN
CLKFB
RST
CLKIN
CLKFB
RST
Figure 28
Figure 29
CLKDLL
CLKDLL
LOCKED
LOCKED
CLK180
CLK270
CLK180
CLK270
CLKDV
CLKDV
CLK2X
CLK2X
CLK90
CLK90
CLK0
CLK0
resembles the BUFGDLL
implements a 2x clock
Figure
BUFG
BUFG
OBUF
BUFG
OBUF
30, a 4x clock
DS001_28_061200
DS001_29_061200
www.xilinx.com
If other clock output is needed, the clock could access a
BUFG only if the DLLs are constrained to exist on opposite
edges (Top or Bottom) of the device.
When using this circuit it is vital to use the SRL16 cell to
reset the second DLL after the initial chip reset. If this is not
done, the second DLL may not recognize the change of
frequencies from when the input changes from a 1x (25/75)
waveform to a 2x (50/50) waveform. It is not recommended
to cascade more than two DLLs.
For design examples and more information on using the
DLL, see
FPGAs.
IBUFG
Spartan-II FPGA Family: Functional Description
Figure 30: DLL Generation of 4x Clock
XAPP174
RST
RST
CLKIN
CLKFB
CLKIN
CLKFB
CLKDLL
CLKDLL
, Using Delay-Locked Loops in Spartan-II
LOCKED
LOCKED
CLK180
CLK270
CLK180
CLK270
CLKDV
CLKDV
CLK2X
CLK2X
CLK90
CLK90
CLK0
CLK0
BUFG
BUFG
OBUF
D
A3
A2
A1
A0
SRL16
WCLK
Module 2 of 4
DS001_30_061200
Q
INV
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