XC2S100-5CS144I XILINX [Xilinx, Inc], XC2S100-5CS144I Datasheet - Page 20

• Manufacturer Part Number: XC2S100-5CS144I
• Description: Spartan-II FPGA Family
• Manufacturer: XILINX [Xilinx, Inc]

By default, these operations are synchronized to CCLK.
The entire start-up sequence lasts eight cycles, called
C0-C7, after which the loaded design is fully functional. The
default timing for start-up is shown in the top half of
Figure
any CCLK cycle C1-C6 through settings in the Xilinx
software. Heavy lines show default settings.
The bottom half of
used version of the start-up timing known as
Sync-to-DONE. This version makes the GTS, GSR, and
GWE events conditional upon the DONE pin going High.
This timing is important for a daisy chain of multiple FPGAs
in serial mode, since it ensures that all FPGAs go through
start-up together, after all their DONE pins have gone High.
Sync-to-DONE timing is selected by setting the GTS, GSR,
and GWE cycles to a value of DONE in the configuration
options. This causes these signals to transition one clock
cycle after DONE externally transitions High.
DS001-2 (v2.8) June 13, 2008
Product Specification
Start-up CLK
Start-up CLK
13. The four operations can be selected to switch on
R
Phase
DONE
Phase
DONE
Figure 13: Start-Up Waveforms
GWE
GWE
GSR
GSR
GTS
GTS
Figure 13
DONE High
0
0
1
1
Default Cycles
Sync to DONE
shows another commonly
2
2
3
3
4
4
5
5
DS001_13_090600
6 7
6 7
www.xilinx.com
Serial Modes
There are two serial configuration modes: In Master Serial
mode, the FPGA controls the configuration process by
driving CCLK as an output. In Slave Serial mode, the FPGA
passively receives CCLK as an input from an external agent
(e.g., a microprocessor, CPLD, or second FPGA in master
mode) that is controlling the configuration process. In both
modes, the FPGA is configured by loading one bit per
CCLK cycle. The MSB of each configuration data byte is
always written to the DIN pin first.
See
Spartan-II FPGA serially. This is an expansion of the "Load
Configuration Data Frames" block in
CS and WRITE normally are not used during serial
configuration. To ensure successful loading of the FPGA,
do not toggle WRITE with CS Low during serial
configuration.
Figure 14: Loading Serial Mode Configuration Data
Figure 14
Spartan-II FPGA Family: Functional Description
for the sequence for loading data into the
CCLK Rising Edge
To CRC Check
User Load One
Configuration
Configuration
Goes High
Bit on Next
After INIT
Data File?
End of
Yes
No
Figure
DS001_14_042403
11. Note that
Module 2 of 4
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