AT94S10AL ATMEL [ATMEL Corporation], AT94S10AL Datasheet - Page 15

• Manufacturer Part Number: AT94S10AL
• Description: Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller,up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM
• Manufacturer: ATMEL [ATMEL Corporation]

Security Bit
AT17LV512/010 Security Bit
Programming
Disabling the Security Bit
Enabling the Security Bit
Verifying the Security Bit
2314D–FPSLI–2/04
.
Secure FPSLIC Configurator Pin Configurations
Once the security bit is programmed, data will no longer output from the normal data
pad. Once the fuse is set, any attempt to erase the fuse will cause the configurator to
erase all of it contents.
Write 4 bytes “00 00 00 00” to addresses 800000-800003 twice, without a power cycle in
between, using the previously defined 2-wire write algorithm.
Write 4 bytes “FF FF FF FF” to addresses 800000-800003 using the previously defined
2-wire write algorithm.
Read 4 bytes of data from addresses 800000-800003 using the previously defined 2-
wire Random Read algorithm. If the data is “FF FF FF FF”, the security bit has been
enabled. If the data is “00 00 00 00”, the security bit has been disabled.
144-pin
LQFP
105
107
53
72
81
CABGA
256-pin
D16
C16
N16
M5
K9
RESET/O
SER_EN
Name
cSDA
cSCK
CE
E
I/O
I/O
O
I
I
I
Description
Three-state DATA output for configuration.
Open-collector bi-directional pin for
programming.
CLOCK output. Used to increment the internal
address and bit counter for reading and
programming.
RESET/OE input (when SER_EN is High). A
Low level on both the CE and RESET/OE
inputs enables the data output driver. A High
level on RESET/OE resets both the address
and bit counters. The logic polarity of this input
is programmable as either RESET/OE or
RESET/OE. This document describes the pin
as RESET/OE.
Chip Enable input. Used for device selection
only when SER_EN is High. A Low level on
both CE and OE enables the data output
driver. A High level on CE disables both the
address and bit counters and forces the device
into a low-power mode. Note this pin will not
enable/disable the device in the 2-wire Serial
mode (i.e., when SER_EN is driven Low).
Serial enable is normally High during FPGA
loading operations. Bringing SER_EN Low
enables the programming mode.
AT94S Secure Family
15