AT94S10AL ATMEL [ATMEL Corporation], AT94S10AL Datasheet - Page 6

• Manufacturer Part Number: AT94S10AL
• Description: Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller,up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM
• Manufacturer: ATMEL [ATMEL Corporation]

Bit Ordering Protocol
Device Address Byte
Figure 2. Start and Stop Conditions
Device Address Byte
EEPROM Address
6
cSCK
cSDA
Where:R/W = 1 Read
MSB
1st
0
MSB
1st
1
2nd 3rd 4th 5th 6th 7th
0
AT94S Secure Family
0
= 0 Write
0
Byte Order
0
Byte n
2nd
0
0
0
8th Bit
LSB
A
8th
E16
ACK
The most significant bit is the first bit of a byte transmitted on the cSDA line for the
Device Address Byte and the EEPROM Address Bytes. It is followed by the lesser sig-
nificant bits until the eighth bit, the least significant bit, is transmitted. However, for Data
Bytes (both writing and reading), the first bit transmitted is the least significant bit. This
protocol is shown in the diagrams below.
The contents of the Device Address Byte are shown below, along with the order in which
the bits are clocked into the device.
The CE pin cannot be used for device selection in programming mode (i.e., when
SER_EN is drive Low).
The EEPROM Address consists of three bytes on the 1-Mbit part. Each Address Byte is
followed by an Acknowledge Bit (provided by the Configurator). These bytes define the
normal address space of the Configurator. The order in which each byte is clocked into
the Configurator is also indicated. Unused bits in an Address Byte must be set to “0”.
Exceptions to this are when reading Device and Manufacturer Codes.
3rd
1
ACK BIT
MSB
A
1st
E15
A
2nd
E14
A
3rd
E13
Condition
4th
STOP
0
A
4th
E12
A
5th
E11
A
6th
E10
A
7th
5th
E9
0
LSB
A
8th
E8
ACK
t WR
MSB
A
1st
E7
6th
1
2nd
A
E6
A
3rd
E5
512-Kbit Address Space
1-Mbit Address Space
Condition
A
4th
START
E4
512-Kbit/1-Mbit Page Length
7th
A
5th
1
E3
A
6th
E2
A
7th
E1
2314D–FPSLI–2/04
LSB
8th
A
LSB
R/W
E0
8th
ACK