AT94S10AL ATMEL [ATMEL Corporation], AT94S10AL Datasheet - Page 9

• Manufacturer Part Number: AT94S10AL
• Description: Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller,up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM
• Manufacturer: ATMEL [ATMEL Corporation]

Data Byte
Writing
2314D–FPSLI–2/04
LSB
1st
D0
2nd
D1
The organization of the Data Byte is shown above. Note that in this case, the Data Byte
is clocked into the device LSB first and MSB last.
Writing to the normal address space takes place in pages. A page is 128-bytes long in
the 1-Mbit part. The page boundaries are, respectively, addresses where A
A
within a page and the number of bytes written must be 128 for the 1-Mbit part. The first
byte is written at the transmitted address. The address is incremented in the Configura-
tor following the receipt of each Data Byte. Only the lower 7 bits of the address are
incremented. Thus, after writing to the last byte address within the given page, the
address will roll over to the first byte address of the same page. A Write Instruction con-
sists of:
WRITE POLLING: On receipt of the Stop Condition, the Configurator enters an inter-
nally-timed write cycle. While the Configurator is busy with this write cycle, it will not
acknowledge any transfers. The programmer can start the next page write by sending
the Start Condition followed by the Device Address, in effect polling the Configurator. If
this is not acknowledged, then the programmer should abandon the transfer without
asserting a Stop Condition. The programmer can then repeatedly initiate a write instruc-
tion as above, until an acknowledge is received. When the Acknowledge Bit is received,
the write instruction should continue by sending the first EEPROM Address Byte to the
Configurator.
An alternative to write polling would be to wait a period of t
page of data or exiting the programming mode. All signals must be maintained during
the entire write cycle.
EOS
3rd
D2
are all zero, and A
a Start Condition
a Device Address Byte with R/W = 0
MS Byte of the EEPROM Address
Next Byte of the EEPROM Address
LS Byte of EEPROM Address
One or more Data Bytes (sent to the
Configurator)
a Stop Condition
An Acknowledge Bit from the Configurator
An Acknowledge Bit from the Configurator
An Acknowledge Bit from the Configurator
An Acknowledge Bit from the Configurator
Each followed by an Acknowledge Bit from the
Configurator
4th
D3
E6
down to A
5th
D4
E0
are all zero. Writing can start at any address
AT94S Secure Family
6th
D5
WR
7th
D6
before sending the next
E0
MSB
8th
D7
down to
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