AT94S10AL ATMEL [ATMEL Corporation], AT94S10AL Datasheet - Page 3

• Manufacturer Part Number: AT94S10AL
• Description: Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller,up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 1. AT94S Architecture
2314D–FPSLI–2/04
Configuration Logic
Configuration
EEPROM
and Chip
For ISP
Erase
I/O
SRAM Memory
Up to 16K x 16
Program
The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by exe-
cuting powerful instructions in a single-clock-cycle, and allows system designers to
optimize power consumption versus processing speed. The AVR core is based on an
enhanced RISC architecture that combines a rich instruction set with 32 general-pur-
pose working registers. All 32 registers are directly connected to the Arithmetic Logic
Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code-efficient while
achieving throughputs up to ten times faster than conventional CISC microcontrollers at
the same clock frequency. The AVR executes out of on-chip SRAM. Both the FPGA
configuration SRAM and AVR instruction code SRAM are automatically loaded at sys-
tem power-up using Atmel’s in-system programmable AT17 Series EEPROM
configuration memories, which are part of the AT94S Multi-chip Module (MCM).
State-of-the-art FPSLIC design tools, System Designer
tion with the FPSLIC architecture to help reduce overall time-to-market by integrating
microcontroller development and debugging, FPGA development, place and route, and
complete system co-verification in one easy-to-use software tool.
Address Lines
Decoded
Up to 16
5 - 40K Gates FPGA
PROGRAMMABLE I/O
Multiply
16K x 8
SRAM
Up to
with
Data
AT94S Secure Family
Timer/Counters
2-wire Serial
16 Prog. I/O
Two Serial
Two 8-bit
™
UARTs
Lines
, were developed in conjunc-
Unit
4 Interrupt Lines
I/O
I/O
I/O
3