CY8C36_1105 CYPRESS [Cypress Semiconductor], CY8C36_1105 Datasheet - Page 19

• Manufacturer Part Number: CY8C36_1105
• Description: Programmable System-on-Chip (PSoC) Multiply and divide instructions
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 4-8. Interrupt Vector Table
Document Number: 001-53413 Rev. *L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
#
function blocks, DMA and
Interrupts 0 to 30
Interrupts form Fixed
from UDBs
LVD
ECC
Reserved
Sleep (Pwr Mgr)
PICU[0]
PICU[1]
PICU[2]
PICU[3]
PICU[4]
PICU[5]
PICU[6]
PICU[12]
PICU[15]
Comparators Combined
Switched Caps Combined
I
CAN
Timer/Counter0
Timer/Counter1
Timer/Counter2
Timer/Counter3
USB SOF Int
Interrupts 0 to
30 from DMA
2
C
UDBs
Interrupts 0 to 30
Function Blocks
from Fixed
Fixed Function
routing logic
to select 31
Interrupt
sources
Global Enable
Figure 4-3. Interrupt Structure
disable bit
Disable, PEND and
Interrupt Enable/
Enable Disable
POST logic
Individual
bits
phub_termout0[0]
phub_termout0[1]
phub_termout0[2]
phub_termout0[3]
phub_termout0[4]
phub_termout0[5]
phub_termout0[6]
phub_termout0[7]
phub_termout0[8]
phub_termout0[9]
phub_termout0[10]
phub_termout0[11]
phub_termout0[12]
phub_termout0[13]
phub_termout0[14]
phub_termout0[15]
phub_termout1[0]
phub_termout1[1]
phub_termout1[2]
phub_termout1[3]
phub_termout1[4]
phub_termout1[5]
30
0
1
interrupts
decoder
8 Level
Priority
for all
DMA
Highest Priority
Interrupt Polling logic
Lowest Priority
PSoC
®
0 to 30
3: CY8C36 Family
udb_intr[0]
udb_intr[1]
udb_intr[2]
udb_intr[3]
udb_intr[4]
udb_intr[5]
udb_intr[6]
udb_intr[7]
udb_intr[8]
udb_intr[9]
udb_intr[10]
udb_intr[11]
udb_intr[12]
udb_intr[13]
udb_intr[14]
udb_intr[15]
udb_intr[16]
udb_intr[17]
udb_intr[18]
udb_intr[19]
udb_intr[20]
udb_intr[21]
[15:0]
IRQ
IRC
IRA
ACTIVE_INT_NUM
INT_VECT_ADDR
Data Sheet
UDB
Page 19 of 126