CY8C36_1105 CYPRESS [Cypress Semiconductor], CY8C36_1105 Datasheet - Page 54

• Manufacturer Part Number: CY8C36_1105
• Description: Programmable System-on-Chip (PSoC) Multiply and divide instructions
• Manufacturer: CYPRESS [Cypress Semiconductor]

valid and available after the fourth conversion, at which time the
EoC signal is generated. To detect the end of conversion, the
system may poll a control register for status or configure the
external EoC signal to generate an interrupt or invoke a DMA
request. When the transfer is done the ADC reenters the standby
state where it stays until another SoC event.
8.2.2.2 Continuous
Continuous sample mode is used to take multiple successive
samples of a single input signal. Multiplexing multiple inputs
should not be done with this mode. There is a latency of three
conversion times before the first conversion result is available.
This is the time required to prime the decimator. After the first
result, successive conversions are available at the selected
sample rate.
8.2.2.3 Multi Sample
Multi sample mode is similar to continuous mode except that the
ADC is reset between samples. This mode is useful when the
input is switched between multiple signals. The decimator is
re-primed between each sample so that previous samples do not
affect the current conversion. Upon completion of a sample, the
next sample is automatically initiated. The results can be
transferred using either firmware polling, interrupt, or DMA.
More information on output formats is provided in the Technical
Reference Manual.
8.2.3 Start of Conversion Input
The SoC signal is used to start an ADC conversion. A digital
clock or UDB output can be used to drive this input. It can be
used when the sampling period must be longer than the ADC
conversion time or when the ADC must be synchronized to other
Document Number: 001-53413 Rev. *L
Routing
Routing
Analog
Analog
From
From
+
_
+
comp2
_
comp0
Figure 8-6. Analog Comparator
4
LUT0
4
4
LUT1
4
UDBs
ANAIF
4
LUT2
4
hardware. This signal is optional and does not need to be
connected if ADC is running in a continuous mode.
8.2.4 End of Conversion Output
The EoC signal goes high at the end of each ADC conversion.
This signal may be used to trigger either an interrupt or DMA
request.
8.3 Comparators
The CY8C36 family of devices contains four comparators in a
device. Comparators have these features:
8.3.1 Input and Output Interface
The positive and negative inputs to the comparators come from
the analog global buses, the analog mux line, the analog local
bus and precision reference through multiplexers. The output
from each comparator could be routed to any of the two input
LUTs. The output of that LUT is routed to the UDB Digital System
Interface.
4
Input offset factory trimmed to less than 5 mV
Rail-to-rail common mode input range (V
Speed and power can be traded off by using one of three
modes: fast, slow, or ultra low-power
Comparator outputs can be routed to lookup tables to perform
simple logic functions and then can also be routed to digital
blocks
The positive input of the comparators may be optionally passed
through a low pass filter. Two filters are provided
Comparator inputs can be connections to GPIO, DAC outputs
and SC block outputs
LUT3
4
comp1
comp3
_
_
+
+
PSoC
Routing
Analog
Routing
From
Analog
From
®
3: CY8C36 Family
SSA
Data Sheet
to V
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