CY8C36_1105 CYPRESS [Cypress Semiconductor], CY8C36_1105 Datasheet - Page 47

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CY8C36_1105

Manufacturer Part Number
CY8C36_1105
Description
Programmable System-on-Chip (PSoC) Multiply and divide instructions
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Figure 7-17. I/O Pin Output Enable Connectivity
7.5.1 CAN Features
Document Number: 001-53413 Rev. *L
4 IO Control Signal Connections from
UDB Array Digital System Interface
CAN2.0A/B protocol implementation – ISO 11898 compliant
Listen Only mode
SW readable error counter and indicator
Sleep mode: Wake the device from sleep with activity on the
Rx pin
Supports two or three wire interface to external transceiver (Tx,
Rx, and Enable). The three-wire interface is compatible with
the Philips PHY; the PHY is not included on-chip. The three
wires can be routed to any I/O
Enhanced interrupt controller
PIN 0
OE
Standard and extended frames with up to 8 bytes of data per
frame
Message filter capabilities
Remote Transmission Request (RTR) support
Programmable bit rate up to 1 Mbps
CAN receive and transmit buffers status
CAN controller error status including BusOff
PIN1
OE
CAN Node 1
PIN2
OE
PSoC
CAN_H
En
CAN Transceiver
CAN Controller
PIN3
Drivers
OE
CAN
Tx Rx
Port i
CAN_L
PIN4
OE
PIN5
OE
Figure 7-18. CAN Bus System Implementation
PIN6
OE
CAN Node 2
CAN_H
PIN7
OE
CAN_L
7.5 CAN
The CAN peripheral is a fully functional CAN supporting
communication baud rates up to 1 Mbps. The CAN controller
implements the CAN2.0A and CAN2.0B specifications as
defined in the Bosch specification and conforms to the
ISO-11898-1 standard. The CAN protocol was originally
designed for automotive applications with a focus on a high level
of fault detection. This ensures high communication reliability at
a low cost. Because of its success in automotive applications,
CAN is used as a standard communication protocol for motion
oriented machine control networks (CANOpen) and factory
automation applications (DeviceNet). The CAN controller
features allow the efficient implementation of higher level
protocols without affecting the performance of the
microcontroller CPU. Full configuration support is provided in
PSoC Creator.
7.5.2 Software Tools Support
CAN Controller configuration integrated into PSoC Creator:
Receive path
Transmit path
CAN Configuration walkthrough with bit timing analyzer
Receive filter setup
16 receive buffers each with its own message filter
Enhanced hardware message filter implementation that
covers the ID, IDE, and RTR
DeviceNet addressing support
Multiple receive buffers linkable to build a larger receive
message array
Automatic transmission request (RTR) response handler
Lost received message notification
Eight transmit buffers
Programmable transmit priority
• Round robin
• Fixed priority
Message transmissions abort capability
CAN Bus
PSoC
CAN Node n
CAN_H
®
3: CY8C36 Family
CAN_L
Data Sheet
Page 47 of 126

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