MC68HC11A1 MOTOROLA [Motorola, Inc], MC68HC11A1 Datasheet - Page 15

• Manufacturer Part Number: MC68HC11A1
• Description: 8-Bit Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

DLY — Enable Oscillator Start-Up Delay on Exit from STOP
CME — Clock Monitor Enable
CR1, CR0 — COP Timer Rate Select
COPRST — Arm/Reset COP Timer Circuitry
HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous
RBOOT — Read Bootstrap ROM Bits 7–4
SMOD — Special Mode Select
MDA — Mode Select A
IRV — Internal Read Visibility
PSEL[3:0] — Priority Select Bits 3 through 0
MC68HC11A8
MC68HC11A8TS/D
RESET:
RESET:
Write $55 to COPRST to arm COP watchdog clearing mechanism. Write $AA to COPRST to reset COP
watchdog.
Refer to 2 Operating Modes and Memory Maps .
Refer to 2 Operating Modes and Memory Maps .
Refer to 2 Operating Modes and Memory Maps .
Refer to 2 Operating Modes and Memory Maps .
Can be written only while the I bit in the CCR is set (interrupts disabled). These bits select one interrupt
source to be elevated above all other I-bit related sources.
CR [1:0]
0 = No stabilization delay on exit from STOP
1 = Stabilization delay enabled on exit from STOP
0 = Clock monitor disabled; slow clocks can be used
1 = Slow or stopped clocks cause clock failure reset
0 0
0 1
1 0
1 1
RBOOT
Bit 7
Bit 7
—
7
0
SMOD
Divide
E/2
—
E =
By
6
6
0
6
16
64
1
4
15
MDA
—
5
5
0
5
XTAL = 4.0 Mhz
–0/+32.8 ms
131.072 ms
524.288 ms
32.768 ms
2.097 sec
Timeout
1.0 MHz
IRV
—
4
4
0
4
PSEL3
3
3
0
3
0
PSEL2
XTAL = 8.0 MHz
–0/+16.4 ms
2
2
0
2
1
262.140 ms
16.384 ms
65.536 ms
1.049 sec
Timeout
2.0 MHz
PSEL1
1
1
0
1
0
$103A
$103C
PSEL0
Bit 0
Bit 0
0
0
1
XTAL = 12.0 MHz
–0/+10.9 ms
10.923 ms
43.691 ms
174.76 ms
699.05 ms
Timeout
3.0 MHz
MOTOROLA
15