PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 180

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

5.5.3
HDLC channel 1 offers the flexibility to connect data during certain time slots, as defined
by registers RTR(4:1) and TTR(4:1), to the RFIFO and XFIFO, respectively. Any
combinations of time slots can be programmed for the receive and transmit directions. If
CCR1.EITS = 1 the selected time slots (RTR(4:1)) are stored in the RFIFO of the
signaling controller and the XFIFO contents is inserted into the transmit path as
controlled by registers TTR(4:1).
For HDLC channels 2 and 3, one out of 24 time slots can be selected for each channel,
but in common for transmit and receive direction.
Within selected time slots single bit positions can be masked to be used/not used for
HDLC transmission for all HDLC channels. Additionally, the use of even, odd or both
frames can be selected for each HDLC channel individually.
Table 45
Receive
Time Slot
Register
RTR 1.7
RTR 1.6
RTR 1.5
RTR 1.4
RTR 1.3
RTR 1.2
RTR 1.1
RTR 1.0
RTR 2.7
RTR 2.6
RTR 2.5
RTR 2.4
RTR 2.3
RTR 2.2
RTR 2.1
RTR 2.0
Data Sheet
Time Slot Assigner (T1/J1)
Time Slot Assigner HDLC Channel 1 (T1/J1)
Transmit
Time Slot
Register
TTR 1.7
TTR 1.6
TTR 1.5
TTR 1.4
TTR 1.3
TTR 1.2
TTR 1.1
TTR 1.0
TTR 2.7
TTR 2.6
TTR 2.5
TTR 2.4
TTR 2.3
TTR 2.2
TTR 2.1
TTR 2.0
Time Slots
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
180
Receive
Time Slot
Register
RTR 3.7
RTR 3.6
RTR 3.5
RTR 3.4
RTR 3.3
RTR 3.2
RTR 3.1
RTR 3.0
RTR 4.7
RTR 4.6
RTR 4.5
RTR 4.4
RTR 4.3
RTR 4.2
RTR 4.1
RTR 4.0
Functional Description T1/J1
Transmit
Time Slot
Register
TTR 3.7
TTR 3.6
TTR 3.5
TTR 3.4
TTR 3.3
TTR 3.2
TTR 3.1
TTR 3.0
TTR 4.7
TTR 4.6
TTR 4.5
TTR 4.4
TTR 4.3
TTR 4.2
TTR 4.1
TTR 4.0
FALC56 V1.2
Time Slots
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PEB 2256
2002-08-27