PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 266

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Port Configuration 5 (Read/Write)
Value after reset: 00
PC5
CCLK2
CCLK1
Data Sheet
7
0011 = TCLK: Transmit Clock (Input)
0100 = XMFB: Transmit Multiframe Begin (Output)
0101 = XSIGM: Transmit Signaling Marker (Output)
0110 = DLX: Data Link Bit Transmit (Output)
0111 = XCLK: Transmit Line Clock (Output)
1000 = XLT: Transmit Line Tristate (Input)
Configure CLK2 Port
0 =
1 =
Configure CLK1 Port
0 =
1 =
H
CLK2 is input
CLK2 is output (only, if DCO-X is active)
CLK1 is input
CLK1 is output (only, if DCO-R is active)
highway. Optionally sampling of XSIG data is controlled by
the active high XSIGM marker.
A 2.048/8.192 MHz clock has to be sourced by the system if
the internal generated transmit clock (DCO-X) is not used.
Optionally this input is used as a synchronization clock for the
DCO-X circuitry with a frequency of 2.048 MHz.
Marks the beginning of every transmit multiframe.
Marks the time slots which are defined by register TTR(4:1) of
every frame on port XDI.
Marks the S
Frequency: 2.048 MHz
With a high level on this port the transmit lines XL1/2 or
XDOP/N are set directly into tristate. This pin function is
logically ored with register XPM2.XLT.
CCLK2
CCLK1
a
-bits within the data stream on XDI.
266
CXMFS
0
CSRP
FALC56 V1.2
CRP
E1 Registers
0
PEB 2256
2002-08-27
(84)